static DEFINE_MUTEX(mdss_mdp_ctl_lock);
-static inline u32 mdss_mdp_get_pclk_rate(struct mdss_mdp_ctl *ctl)
+static inline u64 mdss_mdp_get_pclk_rate(struct mdss_mdp_ctl *ctl)
{
struct mdss_panel_info *pinfo = &ctl->panel_data->panel_info;
perf->prefill_bytes += tmp.prefill_bytes;
if (ctl->intf_type) {
- u32 clk_rate = mdss_mdp_get_pclk_rate(ctl);
+ u64 clk_rate = mdss_mdp_get_pclk_rate(ctl);
/* minimum clock rate due to inefficiency in 3dmux */
- clk_rate = mult_frac(clk_rate >> 1, 9, 8);
+ clk_rate = DIV_ROUND_UP_ULL((clk_rate >> 1) * 9, 8);
if (clk_rate > perf->mdp_clk_rate)
perf->mdp_clk_rate = clk_rate;
}
ktime_t *wakeup_time)
{
struct mdss_panel_info *pinfo;
- u32 clk_rate, clk_period;
+ u64 clk_rate;
+ u32 clk_period;
u32 current_line, total_line;
u32 time_of_line, time_to_vsync, adjust_line_ns;
clk_rate = mdss_mdp_get_pclk_rate(ctl);
- clk_rate /= 1000; /* in kHz */
+ clk_rate = DIV_ROUND_UP_ULL(clk_rate, 1000); /* in kHz */
if (!clk_rate)
return -EINVAL;
* accuracy with high pclk rate and this number is in 17 bit
* range.
*/
- clk_period = 1000000000 / clk_rate;
+ clk_period = DIV_ROUND_UP_ULL(1000000000, clk_rate);
if (!clk_period)
return -EINVAL;
*wakeup_time = ktime_add_ns(current_time, time_to_vsync);
- pr_debug("clk_rate=%dkHz clk_period=%d cur_line=%d tot_line=%d\n",
+ pr_debug("clk_rate=%lldkHz clk_period=%d cur_line=%d tot_line=%d\n",
clk_rate, clk_period, current_line, total_line);
pr_debug("time_to_vsync=%d current_time=%d wakeup_time=%d\n",
time_to_vsync, (int)ktime_to_ms(current_time),
struct mdss_mdp_ctl *ctl = data;
struct mdss_panel_info *pinfo;
u32 line_cnt, min_ln_cnt, active_lns_cnt;
- u32 clk_rate, clk_period, time_of_line;
+ u64 clk_rate;
+ u32 clk_period, time_of_line;
u32 delay;
if (!data) {
pinfo->mipi.dsi_pclk_rate :
pinfo->clk_rate);
- clk_rate /= 1000; /* in kHz */
+ clk_rate = DIV_ROUND_UP_ULL(clk_rate, 1000); /* in kHz */
if (!clk_rate) {
pr_err("Unable to get proper clk_rate\n");
return;
* accuracy with high pclk rate and this number is in 17 bit
* range.
*/
- clk_period = 1000000000 / clk_rate;
+ clk_period = DIV_ROUND_UP_ULL(1000000000, clk_rate);
if (!clk_period) {
pr_err("Unable to calculate clock period\n");
return;
(u32 *)&debugfs_info->panel_info.min_fps);
debugfs_create_u32("max_refresh_rate", 0644, debugfs_info->root,
(u32 *)&debugfs_info->panel_info.max_fps);
- debugfs_create_u32("clk_rate", 0644, debugfs_info->root,
- (u32 *)&debugfs_info->panel_info.clk_rate);
+ debugfs_create_u64("clk_rate", 0644, debugfs_info->root,
+ (u64 *)&debugfs_info->panel_info.clk_rate);
debugfs_create_u32("bl_min", 0644, debugfs_info->root,
(u32 *)&debugfs_info->panel_info.bl_min);
debugfs_create_u32("bl_max", 0644, debugfs_info->root,