/* VMOV scalar to general purpose register */
TCGv_i32 tmp;
- /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
- if (a->size == MO_32
- ? !dc_isar_feature(aa32_fpsp_v2, s)
- : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
+ /*
+ * SIZE == MO_32 is a VFP instruction; otherwise NEON. MVE has
+ * all sizes, whether the CPU has fp or not.
+ */
+ if (!dc_isar_feature(aa32_mve, s)) {
+ if (a->size == MO_32
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
}
/* UNDEF accesses to D16-D31 if they don't exist */
/* VMOV general purpose register to scalar */
TCGv_i32 tmp;
- /* SIZE == MO_32 is a VFP instruction; otherwise NEON. */
- if (a->size == MO_32
- ? !dc_isar_feature(aa32_fpsp_v2, s)
- : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
- return false;
+ /*
+ * SIZE == MO_32 is a VFP instruction; otherwise NEON. MVE has
+ * all sizes, whether the CPU has fp or not.
+ */
+ if (!dc_isar_feature(aa32_mve, s)) {
+ if (a->size == MO_32
+ ? !dc_isar_feature(aa32_fpsp_v2, s)
+ : !arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
}
/* UNDEF accesses to D16-D31 if they don't exist */
static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
{
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return FPSysRegCheckFailed;
}
{
TCGv_i32 tmp;
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return false;
}
{
TCGv_i32 tmp;
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return false;
}
* floating point register. Note that this does not require support
* for double precision arithmetic.
*/
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return false;
}
uint32_t offset;
TCGv_i32 addr, tmp;
- if (!dc_isar_feature(aa32_fp16_arith, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return false;
}
uint32_t offset;
TCGv_i32 addr, tmp;
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return false;
}
TCGv_i64 tmp;
/* Note that this does not require support for double arithmetic. */
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return false;
}
TCGv_i32 addr, tmp;
int i, n;
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return false;
}
int i, n;
/* Note that this does not require support for double arithmetic. */
- if (!dc_isar_feature(aa32_fpsp_v2, s)) {
+ if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
return false;
}