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riscv, bpf: Support sign-extension mov insns
author
Pu Lehui
<pulehui@huawei.com>
Thu, 24 Aug 2023 09:49:57 +0000
(09:49 +0000)
committer
Alexei Starovoitov
<ast@kernel.org>
Thu, 24 Aug 2023 16:13:08 +0000
(09:13 -0700)
Add support sign-extension mov instructions for RV64.
Signed-off-by: Pu Lehui <pulehui@huawei.com>
Acked-by: Björn Töpel <bjorn@kernel.org>
Link:
https://lore.kernel.org/r/20230824095001.3408573-4-pulehui@huaweicloud.com
Signed-off-by: Alexei Starovoitov <ast@kernel.org>
arch/riscv/net/bpf_jit_comp64.c
patch
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diff --git
a/arch/riscv/net/bpf_jit_comp64.c
b/arch/riscv/net/bpf_jit_comp64.c
index
fd36cb1
..
bcf1e75
100644
(file)
--- a/
arch/riscv/net/bpf_jit_comp64.c
+++ b/
arch/riscv/net/bpf_jit_comp64.c
@@
-1047,7
+1047,19
@@
int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
emit_zext_32(rd, ctx);
break;
}
- emit_mv(rd, rs, ctx);
+ switch (insn->off) {
+ case 0:
+ emit_mv(rd, rs, ctx);
+ break;
+ case 8:
+ case 16:
+ emit_slli(RV_REG_T1, rs, 64 - insn->off, ctx);
+ emit_srai(rd, RV_REG_T1, 64 - insn->off, ctx);
+ break;
+ case 32:
+ emit_addiw(rd, rs, 0, ctx);
+ break;
+ }
if (!is64 && !aux->verifier_zext)
emit_zext_32(rd, ctx);
break;