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[MIPS] SMTC: The MT ASE requires to initialize c0_pagemask and c0_wired.
authorRalf Baechle <ralf@linux-mips.org>
Thu, 31 May 2007 13:03:45 +0000 (14:03 +0100)
committerRalf Baechle <ralf@linux-mips.org>
Mon, 11 Jun 2007 17:20:54 +0000 (18:20 +0100)
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/kernel/traps.c

index 44f0a2c..a7a17eb 100644 (file)
@@ -1384,6 +1384,13 @@ void __init per_cpu_trap_init(void)
                cpu_cache_init();
                tlb_init();
 #ifdef CONFIG_MIPS_MT_SMTC
+       } else if (!secondaryTC) {
+               /*
+                * First TC in non-boot VPE must do subset of tlb_init()
+                * for MMU countrol registers.
+                */
+               write_c0_pagemask(PM_DEFAULT_MASK);
+               write_c0_wired(0);
        }
 #endif /* CONFIG_MIPS_MT_SMTC */
 }