#set_location_assignment PIN_AA1 -to dbg_ppu_clk\r
#set_location_assignment PIN_W2 -to dbg_mem_clk\r
\r
+#global clock.\r
+set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to pi_base_clk\r
\r
#project files\r
-\r
-\r
-set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
-set_global_assignment -name VHDL_FILE mem/ram.vhd\r
+#set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
+#set_global_assignment -name VHDL_FILE mem/ram.vhd\r
set_global_assignment -name VHDL_FILE chip_selector.vhd\r
-set_global_assignment -name VHDL_FILE dummy-mos6502.vhd\r
+#set_global_assignment -name VHDL_FILE dummy-mos6502.vhd\r
set_global_assignment -name VHDL_FILE ppu/render.vhd\r
-set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
+#set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r
\r
set_global_assignment -name VHDL_FILE de0_cv_nes.vhd\r
\r
\r
##timing definition...\r
-set_global_assignment -name SDC_FILE mos6502-timing.sdc\r
-set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to base_clk\r
-\r
-##for signal trap ii setting...\r
-#set_global_assignment -name ENABLE_SIGNALTAP ON\r
-#set_global_assignment -name USE_SIGNALTAP_FILE "de0-cv-analyze-all.stp"\r
-#set_global_assignment -name SIGNALTAP_FILE "de0-cv-analyze-all.stp"\r
-\r
+set_global_assignment -name SDC_FILE "mos6502-timing.sdc"\r
+\r
+#for signal trap ii setting...\r
+set_global_assignment -name ENABLE_SIGNALTAP ON\r
+set_global_assignment -name USE_SIGNALTAP_FILE "de0-cv-analyze-all.stp"\r
+set_global_assignment -name SIGNALTAP_FILE "de0-cv-analyze-all.stp"\r
+\r
+set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to dbg_base_clk -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to pi_base_clk -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to pi_base_clk -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to pi_rst_n -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to po_b[0] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to po_b[1] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to po_b[2] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to po_b[3] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to po_g[0] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to po_g[1] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to po_g[2] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to po_g[3] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to po_h_sync_n -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to po_r[0] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to po_r[1] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to po_r[2] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to po_r[3] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to po_v_sync_n -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "render:render_inst|reg_nes_x[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "render:render_inst|reg_nes_x[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "render:render_inst|reg_nes_x[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "render:render_inst|reg_nes_x[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "render:render_inst|reg_nes_x[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "render:render_inst|reg_nes_x[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "render:render_inst|reg_nes_x[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "render:render_inst|reg_nes_x[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "render:render_inst|reg_nes_x[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "render:render_inst|reg_nes_y[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "render:render_inst|reg_nes_y[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "render:render_inst|reg_nes_y[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "render:render_inst|reg_nes_y[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "render:render_inst|reg_nes_y[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "render:render_inst|reg_nes_y[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "render:render_inst|reg_nes_y[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "render:render_inst|reg_nes_y[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "render:render_inst|reg_nes_y[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "render:render_inst|reg_vga_x[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "render:render_inst|reg_vga_x[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "render:render_inst|reg_vga_x[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "render:render_inst|reg_vga_x[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "render:render_inst|reg_vga_x[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "render:render_inst|reg_vga_x[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "render:render_inst|reg_vga_x[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "render:render_inst|reg_vga_x[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "render:render_inst|reg_vga_x[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "render:render_inst|reg_vga_x[9]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "render:render_inst|reg_vga_y[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "render:render_inst|reg_vga_y[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "render:render_inst|reg_vga_y[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "render:render_inst|reg_vga_y[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "render:render_inst|reg_vga_y[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "render:render_inst|reg_vga_y[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "render:render_inst|reg_vga_y[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "render:render_inst|reg_vga_y[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "render:render_inst|reg_vga_y[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "render:render_inst|reg_vga_y[9]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to pi_rst_n -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to po_b[0] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to po_b[1] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to po_b[2] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to po_b[3] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to po_g[0] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to po_g[1] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to po_g[2] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to po_g[3] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to po_h_sync_n -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to po_r[0] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to po_r[1] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to po_r[2] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to po_r[3] -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to po_v_sync_n -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "render:render_inst|reg_nes_x[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "render:render_inst|reg_nes_x[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "render:render_inst|reg_nes_x[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "render:render_inst|reg_nes_x[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "render:render_inst|reg_nes_x[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "render:render_inst|reg_nes_x[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "render:render_inst|reg_nes_x[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "render:render_inst|reg_nes_x[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "render:render_inst|reg_nes_x[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "render:render_inst|reg_nes_y[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "render:render_inst|reg_nes_y[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "render:render_inst|reg_nes_y[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "render:render_inst|reg_nes_y[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "render:render_inst|reg_nes_y[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "render:render_inst|reg_nes_y[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "render:render_inst|reg_nes_y[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "render:render_inst|reg_nes_y[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "render:render_inst|reg_nes_y[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "render:render_inst|reg_vga_x[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "render:render_inst|reg_vga_x[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "render:render_inst|reg_vga_x[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "render:render_inst|reg_vga_x[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "render:render_inst|reg_vga_x[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "render:render_inst|reg_vga_x[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "render:render_inst|reg_vga_x[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "render:render_inst|reg_vga_x[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "render:render_inst|reg_vga_x[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "render:render_inst|reg_vga_x[9]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "render:render_inst|reg_vga_y[0]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "render:render_inst|reg_vga_y[1]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "render:render_inst|reg_vga_y[2]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "render:render_inst|reg_vga_y[3]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "render:render_inst|reg_vga_y[4]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "render:render_inst|reg_vga_y[5]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "render:render_inst|reg_vga_y[6]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "render:render_inst|reg_vga_y[7]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "render:render_inst|reg_vga_y[8]" -section_id auto_signaltap_0\r
+set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "render:render_inst|reg_vga_y[9]" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=54" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=54" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=21163" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=189" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=8192" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=19982" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=8192" -section_id auto_signaltap_0\r
+set_global_assignment -name SLD_FILE "de0-cv-analyze-all_auto_stripped.stp"\r
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
if ((pi_rnd_en(0) or pi_rnd_en(2))= '1') then\r
if (reg_vga_x = VGA_W_MAX - 1) then\r
reg_vga_x <= 0;\r
+ reg_nes_x <= 0;\r
if (reg_vga_x = VGA_H_MAX - 1) then\r
reg_vga_y <= 0;\r
+ reg_nes_y <= 0;\r
else\r
reg_vga_y <= reg_vga_y + 1;\r
+ reg_nes_y <= (reg_vga_y + 1) / 2;\r
end if;\r
else\r
reg_vga_x <= reg_vga_x + 1;\r
+ reg_nes_x <= (reg_vga_x + 1) / 2;\r
end if;\r
\r
--sync signal assert.\r
end if;\r
end if;--if (pi_rnd_en(1) = '1' or pi_rnd_en(3) = '1' ) then\r
\r
- --nes x/y position...\r
- reg_nes_x <= reg_vga_x / 2;\r
- reg_nes_y <= reg_vga_y / 2;\r
-\r
--pre-fetch x/y position...\r
if (reg_vga_x < HSCAN_NEXT_START * 2) then\r
reg_prf_x <= reg_vga_x / 2 + conv_integer(pi_ppu_scroll_x) + PREFETCH_INT;\r
end if;--if (pi_rst_n = '0') then\r
end process;\r
\r
- --vram access state machine (state transition)...\r
- vac_set_stat_p : process (pi_rst_n, pi_base_clk)\r
- begin\r
- if (pi_rst_n = '0') then\r
- reg_v_cur_state <= IDLE;\r
- elsif (rising_edge(pi_base_clk)) then\r
- reg_v_cur_state <= reg_v_next_state;\r
- end if;--if (pi_rst_n = '0') then\r
- end process;\r
-\r
- --state change to next.\r
- vac_next_stat_p : process (reg_v_cur_state, pi_rnd_en, pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y)\r
-function bg_process (\r
- pm_sbg : in std_logic;\r
- pm_nes_x : in integer range 0 to VGA_W_MAX - 1;\r
- pm_nes_y : in integer range 0 to VGA_H_MAX - 1\r
- )return integer is\r
-begin\r
- if (pm_sbg = '1'and\r
- (pm_nes_x <= HSCAN or pm_nes_x >= HSCAN_NEXT_START) and\r
- (pm_nes_y < VSCAN or pm_nes_y = VSCAN_NEXT_START)) then\r
- return 1;\r
- else\r
- return 0;\r
- end if;\r
-end;\r
-\r
-function is_idle (\r
- pm_sbg : in std_logic;\r
- pm_nes_x : in integer range 0 to VGA_W_MAX - 1;\r
- pm_nes_y : in integer range 0 to VGA_H_MAX - 1\r
- )return integer is\r
-begin\r
- if (pm_sbg = '0' or\r
- (pm_nes_x > HSCAN and pm_nes_x < HSCAN_NEXT_START) or\r
- (pm_nes_y >= VSCAN and pm_nes_y < VSCAN_NEXT_START)) then\r
- return 1;\r
- else\r
- return 0;\r
- end if;\r
-end;\r
- begin\r
- case reg_v_cur_state is\r
- when IDLE =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(3) = '1' and\r
- reg_nes_x mod 8 = 0) then\r
- --start vram access process.\r
- reg_v_next_state <= AD_SET0;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- when AD_SET0 =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(0) = '1'\r
- ) then\r
- reg_v_next_state <= AD_SET1;\r
- elsif (is_idle(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
- ---when nes_x=257, fall to idle\r
- reg_v_next_state <= IDLE;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- when AD_SET1 =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(1) = '1'\r
- ) then\r
- reg_v_next_state <= AD_SET2;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- when AD_SET2 =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(2) = '1'\r
- ) then\r
- reg_v_next_state <= AD_SET3;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- when AD_SET3 =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(3) = '1'\r
- ) then\r
- reg_v_next_state <= REG_SET0;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- when REG_SET0 =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(0) = '1'\r
- ) then\r
- reg_v_next_state <= REG_SET1;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- when REG_SET1 =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(1) = '1'\r
- ) then\r
- reg_v_next_state <= REG_SET2;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- when REG_SET2 =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(2) = '1'\r
- ) then\r
- reg_v_next_state <= REG_SET3;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- when REG_SET3 =>\r
- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
- pi_rnd_en(3) = '1'\r
- ) then\r
- reg_v_next_state <= AD_SET0;\r
- else\r
- reg_v_next_state <= reg_v_cur_state;\r
- end if;\r
- end case;\r
- end process;\r
-\r
- po_v_ce_n <= reg_v_ce_n;\r
- po_v_rd_n <= reg_v_rd_n;\r
- po_v_wr_n <= reg_v_wr_n;\r
- po_v_addr <= reg_v_addr;\r
-\r
- po_plt_ce_n <= reg_plt_ce_n;\r
- po_plt_rd_n <= reg_plt_rd_n;\r
- po_plt_wr_n <= reg_plt_wr_n;\r
- po_plt_addr <= reg_plt_addr;\r
-\r
- --vram r/w selector state machine...\r
- vac_main_stat_p : process (reg_v_cur_state)\r
- begin\r
- case reg_v_cur_state is\r
- when IDLE =>\r
- reg_v_rd_n <= 'Z';\r
- reg_v_wr_n <= 'Z';\r
- when AD_SET0 | AD_SET1 | REG_SET2 | REG_SET3 =>\r
- reg_v_rd_n <= '1';\r
- reg_v_wr_n <= '1';\r
- when AD_SET2 | AD_SET3 | REG_SET0 | REG_SET1 =>\r
- reg_v_rd_n <= '0';\r
- reg_v_wr_n <= '1';\r
- end case;\r
-\r
- case reg_v_cur_state is\r
- when IDLE =>\r
- reg_v_ce_n <= 'Z';\r
- reg_plt_ce_n <= 'Z';\r
- reg_plt_rd_n <= 'Z';\r
- reg_plt_wr_n <= 'Z'; \r
- when AD_SET0 | AD_SET1 | REG_SET2 | REG_SET3 | AD_SET2 | AD_SET3 | REG_SET0 | REG_SET1 =>\r
- reg_v_ce_n <= '0';\r
- reg_plt_ce_n <= '0';\r
- reg_plt_rd_n <= '0';\r
- reg_plt_wr_n <= '1'; \r
- end case;\r
- end process;\r
-\r
- --vram address state machine...\r
- vaddr_stat_p : process (pi_rst_n, pi_base_clk)\r
- begin\r
- if (pi_rst_n = '0') then\r
- reg_v_addr <= (others => 'Z');\r
- reg_v_data <= (others => 'Z');\r
- reg_disp_nt <= (others => 'Z');\r
- reg_disp_attr <= (others => 'Z');\r
- elsif (rising_edge(pi_base_clk)) then\r
- reg_v_data <= pi_v_data;\r
-\r
- if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
- ----fetch next tile byte.\r
- if (reg_prf_x mod 8 = 1) then\r
- --vram addr is incremented every 8 cycle.\r
- --name table at 0x2000\r
- reg_v_addr(9 downto 0)\r
- <= conv_std_logic_vector(reg_prf_y, 9)(7 downto 3)\r
- & conv_std_logic_vector(reg_prf_x, 9)(7 downto 3);\r
- reg_v_addr(13 downto 10) <= "10" & pi_ppu_ctrl(PPUBNA downto 0)\r
- + ("000" & conv_std_logic_vector(reg_prf_x, 9)(8));\r
- \r
- elsif (reg_prf_x mod 8 = 2 and reg_v_cur_state = REG_SET0) then\r
- reg_disp_nt <= reg_v_data;\r
- \r
- ----fetch attr table byte.\r
- elsif (reg_prf_x mod 8 = 3) then\r
- --attr table at 0x23c0\r
- reg_v_addr(7 downto 0) <= "11000000" +\r
- ("00" & conv_std_logic_vector(reg_prf_y, 9)(7 downto 5)\r
- & conv_std_logic_vector(reg_prf_x, 9)(7 downto 5));\r
- reg_v_addr(13 downto 8) <= "10" &\r
- pi_ppu_ctrl(PPUBNA downto 0) & "11"\r
- + ("000" & conv_std_logic_vector(reg_prf_x, 9)(8) & "00");\r
- \r
- elsif (reg_prf_x mod 8 = 4 and reg_v_cur_state = REG_SET0) then\r
- reg_disp_attr <= reg_v_data;\r
-\r
- ----fetch pattern table low byte.\r
- elsif (reg_prf_x mod 8 = 5) then\r
- --vram addr is incremented every 8 cycle.\r
- reg_v_addr <= "0" & pi_ppu_ctrl(PPUBPA) &\r
- reg_disp_nt(7 downto 0)\r
- & "0" & conv_std_logic_vector(reg_prf_y, 9)(2 downto 0);\r
-\r
- ----fetch pattern table high byte.\r
- elsif (reg_prf_x mod 8 = 7) then\r
- --vram addr is incremented every 8 cycle.\r
- reg_v_addr <= "0" & pi_ppu_ctrl(PPUBPA) &\r
- reg_disp_nt(7 downto 0)\r
- & "0" & conv_std_logic_vector(reg_prf_y, 9)(2 downto 0)\r
- + "00000000001000";\r
- end if;\r
- end if;\r
- end if;--if (pi_rst_n = '0') then\r
- end process;\r
-\r
- --pattern table state machine...\r
- bg_ptn_p : process (pi_rst_n, pi_base_clk)\r
- begin\r
- if (pi_rst_n = '0') then\r
- reg_disp_ptn_l <= (others => '0');\r
- reg_disp_ptn_h <= (others => '0');\r
- elsif (rising_edge(pi_base_clk)) then\r
-\r
- if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
- if (reg_v_cur_state = REG_SET0) then\r
- if (reg_prf_x mod 8 = 6) then\r
- reg_disp_ptn_l <= reg_v_data & reg_disp_ptn_l(7 downto 0);\r
- else\r
- reg_disp_ptn_l <= "0" & reg_disp_ptn_l(15 downto 1);\r
- end if;\r
-\r
- if (reg_prf_x mod 8 = 0) then\r
- reg_disp_ptn_h <= reg_v_data & reg_disp_ptn_h(7 downto 0);\r
- else\r
- reg_disp_ptn_h <= "0" & reg_disp_ptn_h(15 downto 1);\r
- end if;\r
-\r
- elsif (reg_v_cur_state = AD_SET0) then\r
- reg_disp_ptn_l <= "0" & reg_disp_ptn_l(15 downto 1);\r
- reg_disp_ptn_h <= "0" & reg_disp_ptn_h(15 downto 1);\r
-\r
- end if;\r
- end if;\r
- end if;--if (pi_rst_n = '0') then\r
- end process;\r
-\r
- --palette table state machine...\r
- plt_ac_p : process (pi_rst_n, pi_base_clk)\r
- begin\r
- if (pi_rst_n = '0') then\r
- reg_plt_addr <= (others => 'Z');\r
- reg_plt_data <= (others => 'Z');\r
- elsif (rising_edge(pi_base_clk)) then\r
- \r
- reg_plt_data <= pi_plt_data;\r
- \r
- if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
- if (conv_std_logic_vector(reg_nes_y, 9)(4) = '0'\r
- and (reg_disp_ptn_h(0) or reg_disp_ptn_l(0)) = '1') then\r
- reg_plt_addr <=\r
- "0" & reg_disp_attr(1 downto 0) & reg_disp_ptn_h(0) & reg_disp_ptn_l(0);\r
- elsif (conv_std_logic_vector(reg_nes_y, 9)(4) = '1'\r
- and (reg_disp_ptn_h(0) or reg_disp_ptn_l(0)) = '1') then\r
- reg_plt_addr <=\r
- "0" & reg_disp_attr(5 downto 4) & reg_disp_ptn_h(0) & reg_disp_ptn_l(0);\r
- else\r
- ---else: no output color >> universal bg color output.\r
- --0x3f00 is the universal bg palette.\r
- reg_plt_addr <= (others => '0');\r
- end if;\r
- end if;\r
- end if;--if (pi_rst_n = '0') then\r
- end process;\r
+-- --vram access state machine (state transition)...\r
+-- vac_set_stat_p : process (pi_rst_n, pi_base_clk)\r
+-- begin\r
+-- if (pi_rst_n = '0') then\r
+-- reg_v_cur_state <= IDLE;\r
+-- elsif (rising_edge(pi_base_clk)) then\r
+-- reg_v_cur_state <= reg_v_next_state;\r
+-- end if;--if (pi_rst_n = '0') then\r
+-- end process;\r
+--\r
+-- --state change to next.\r
+-- vac_next_stat_p : process (reg_v_cur_state, pi_rnd_en, pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y)\r
+--function bg_process (\r
+-- pm_sbg : in std_logic;\r
+-- pm_nes_x : in integer range 0 to VGA_W_MAX - 1;\r
+-- pm_nes_y : in integer range 0 to VGA_H_MAX - 1\r
+-- )return integer is\r
+--begin\r
+-- if (pm_sbg = '1'and\r
+-- (pm_nes_x <= HSCAN or pm_nes_x >= HSCAN_NEXT_START) and\r
+-- (pm_nes_y < VSCAN or pm_nes_y = VSCAN_NEXT_START)) then\r
+-- return 1;\r
+-- else\r
+-- return 0;\r
+-- end if;\r
+--end;\r
+--\r
+--function is_idle (\r
+-- pm_sbg : in std_logic;\r
+-- pm_nes_x : in integer range 0 to VGA_W_MAX - 1;\r
+-- pm_nes_y : in integer range 0 to VGA_H_MAX - 1\r
+-- )return integer is\r
+--begin\r
+-- if (pm_sbg = '0' or\r
+-- (pm_nes_x > HSCAN and pm_nes_x < HSCAN_NEXT_START) or\r
+-- (pm_nes_y >= VSCAN and pm_nes_y < VSCAN_NEXT_START)) then\r
+-- return 1;\r
+-- else\r
+-- return 0;\r
+-- end if;\r
+--end;\r
+-- begin\r
+-- case reg_v_cur_state is\r
+-- when IDLE =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(3) = '1' and\r
+-- reg_nes_x mod 8 = 0) then\r
+-- --start vram access process.\r
+-- reg_v_next_state <= AD_SET0;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- when AD_SET0 =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(0) = '1'\r
+-- ) then\r
+-- reg_v_next_state <= AD_SET1;\r
+-- elsif (is_idle(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
+-- ---when nes_x=257, fall to idle\r
+-- reg_v_next_state <= IDLE;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- when AD_SET1 =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(1) = '1'\r
+-- ) then\r
+-- reg_v_next_state <= AD_SET2;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- when AD_SET2 =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(2) = '1'\r
+-- ) then\r
+-- reg_v_next_state <= AD_SET3;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- when AD_SET3 =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(3) = '1'\r
+-- ) then\r
+-- reg_v_next_state <= REG_SET0;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- when REG_SET0 =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(0) = '1'\r
+-- ) then\r
+-- reg_v_next_state <= REG_SET1;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- when REG_SET1 =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(1) = '1'\r
+-- ) then\r
+-- reg_v_next_state <= REG_SET2;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- when REG_SET2 =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(2) = '1'\r
+-- ) then\r
+-- reg_v_next_state <= REG_SET3;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- when REG_SET3 =>\r
+-- if (bg_process(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1 and\r
+-- pi_rnd_en(3) = '1'\r
+-- ) then\r
+-- reg_v_next_state <= AD_SET0;\r
+-- else\r
+-- reg_v_next_state <= reg_v_cur_state;\r
+-- end if;\r
+-- end case;\r
+-- end process;\r
+--\r
+-- po_v_ce_n <= reg_v_ce_n;\r
+-- po_v_rd_n <= reg_v_rd_n;\r
+-- po_v_wr_n <= reg_v_wr_n;\r
+-- po_v_addr <= reg_v_addr;\r
+--\r
+-- po_plt_ce_n <= reg_plt_ce_n;\r
+-- po_plt_rd_n <= reg_plt_rd_n;\r
+-- po_plt_wr_n <= reg_plt_wr_n;\r
+-- po_plt_addr <= reg_plt_addr;\r
+--\r
+-- --vram r/w selector state machine...\r
+-- vac_main_stat_p : process (reg_v_cur_state)\r
+-- begin\r
+-- case reg_v_cur_state is\r
+-- when IDLE =>\r
+-- reg_v_rd_n <= 'Z';\r
+-- reg_v_wr_n <= 'Z';\r
+-- when AD_SET0 | AD_SET1 | REG_SET2 | REG_SET3 =>\r
+-- reg_v_rd_n <= '1';\r
+-- reg_v_wr_n <= '1';\r
+-- when AD_SET2 | AD_SET3 | REG_SET0 | REG_SET1 =>\r
+-- reg_v_rd_n <= '0';\r
+-- reg_v_wr_n <= '1';\r
+-- end case;\r
+--\r
+-- case reg_v_cur_state is\r
+-- when IDLE =>\r
+-- reg_v_ce_n <= 'Z';\r
+-- reg_plt_ce_n <= 'Z';\r
+-- reg_plt_rd_n <= 'Z';\r
+-- reg_plt_wr_n <= 'Z'; \r
+-- when AD_SET0 | AD_SET1 | REG_SET2 | REG_SET3 | AD_SET2 | AD_SET3 | REG_SET0 | REG_SET1 =>\r
+-- reg_v_ce_n <= '0';\r
+-- reg_plt_ce_n <= '0';\r
+-- reg_plt_rd_n <= '0';\r
+-- reg_plt_wr_n <= '1'; \r
+-- end case;\r
+-- end process;\r
+--\r
+-- --vram address state machine...\r
+-- vaddr_stat_p : process (pi_rst_n, pi_base_clk)\r
+-- begin\r
+-- if (pi_rst_n = '0') then\r
+-- reg_v_addr <= (others => 'Z');\r
+-- reg_v_data <= (others => 'Z');\r
+-- reg_disp_nt <= (others => 'Z');\r
+-- reg_disp_attr <= (others => 'Z');\r
+-- elsif (rising_edge(pi_base_clk)) then\r
+-- reg_v_data <= pi_v_data;\r
+--\r
+-- if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
+-- ----fetch next tile byte.\r
+-- if (reg_prf_x mod 8 = 1) then\r
+-- --vram addr is incremented every 8 cycle.\r
+-- --name table at 0x2000\r
+-- reg_v_addr(9 downto 0)\r
+-- <= conv_std_logic_vector(reg_prf_y, 9)(7 downto 3)\r
+-- & conv_std_logic_vector(reg_prf_x, 9)(7 downto 3);\r
+-- reg_v_addr(13 downto 10) <= "10" & pi_ppu_ctrl(PPUBNA downto 0)\r
+-- + ("000" & conv_std_logic_vector(reg_prf_x, 9)(8));\r
+-- \r
+-- elsif (reg_prf_x mod 8 = 2 and reg_v_cur_state = REG_SET0) then\r
+-- reg_disp_nt <= reg_v_data;\r
+-- \r
+-- ----fetch attr table byte.\r
+-- elsif (reg_prf_x mod 8 = 3) then\r
+-- --attr table at 0x23c0\r
+-- reg_v_addr(7 downto 0) <= "11000000" +\r
+-- ("00" & conv_std_logic_vector(reg_prf_y, 9)(7 downto 5)\r
+-- & conv_std_logic_vector(reg_prf_x, 9)(7 downto 5));\r
+-- reg_v_addr(13 downto 8) <= "10" &\r
+-- pi_ppu_ctrl(PPUBNA downto 0) & "11"\r
+-- + ("000" & conv_std_logic_vector(reg_prf_x, 9)(8) & "00");\r
+-- \r
+-- elsif (reg_prf_x mod 8 = 4 and reg_v_cur_state = REG_SET0) then\r
+-- reg_disp_attr <= reg_v_data;\r
+--\r
+-- ----fetch pattern table low byte.\r
+-- elsif (reg_prf_x mod 8 = 5) then\r
+-- --vram addr is incremented every 8 cycle.\r
+-- reg_v_addr <= "0" & pi_ppu_ctrl(PPUBPA) &\r
+-- reg_disp_nt(7 downto 0)\r
+-- & "0" & conv_std_logic_vector(reg_prf_y, 9)(2 downto 0);\r
+--\r
+-- ----fetch pattern table high byte.\r
+-- elsif (reg_prf_x mod 8 = 7) then\r
+-- --vram addr is incremented every 8 cycle.\r
+-- reg_v_addr <= "0" & pi_ppu_ctrl(PPUBPA) &\r
+-- reg_disp_nt(7 downto 0)\r
+-- & "0" & conv_std_logic_vector(reg_prf_y, 9)(2 downto 0)\r
+-- + "00000000001000";\r
+-- end if;\r
+-- end if;\r
+-- end if;--if (pi_rst_n = '0') then\r
+-- end process;\r
+--\r
+-- --pattern table state machine...\r
+-- bg_ptn_p : process (pi_rst_n, pi_base_clk)\r
+-- begin\r
+-- if (pi_rst_n = '0') then\r
+-- reg_disp_ptn_l <= (others => '0');\r
+-- reg_disp_ptn_h <= (others => '0');\r
+-- elsif (rising_edge(pi_base_clk)) then\r
+--\r
+-- if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
+-- if (reg_v_cur_state = REG_SET0) then\r
+-- if (reg_prf_x mod 8 = 6) then\r
+-- reg_disp_ptn_l <= reg_v_data & reg_disp_ptn_l(7 downto 0);\r
+-- else\r
+-- reg_disp_ptn_l <= "0" & reg_disp_ptn_l(15 downto 1);\r
+-- end if;\r
+--\r
+-- if (reg_prf_x mod 8 = 0) then\r
+-- reg_disp_ptn_h <= reg_v_data & reg_disp_ptn_h(7 downto 0);\r
+-- else\r
+-- reg_disp_ptn_h <= "0" & reg_disp_ptn_h(15 downto 1);\r
+-- end if;\r
+--\r
+-- elsif (reg_v_cur_state = AD_SET0) then\r
+-- reg_disp_ptn_l <= "0" & reg_disp_ptn_l(15 downto 1);\r
+-- reg_disp_ptn_h <= "0" & reg_disp_ptn_h(15 downto 1);\r
+--\r
+-- end if;\r
+-- end if;\r
+-- end if;--if (pi_rst_n = '0') then\r
+-- end process;\r
+--\r
+-- --palette table state machine...\r
+-- plt_ac_p : process (pi_rst_n, pi_base_clk)\r
+-- begin\r
+-- if (pi_rst_n = '0') then\r
+-- reg_plt_addr <= (others => 'Z');\r
+-- reg_plt_data <= (others => 'Z');\r
+-- elsif (rising_edge(pi_base_clk)) then\r
+-- \r
+-- reg_plt_data <= pi_plt_data;\r
+-- \r
+-- if (is_bg(pi_ppu_mask(PPUSBG), reg_nes_x, reg_nes_y) = 1) then\r
+-- if (conv_std_logic_vector(reg_nes_y, 9)(4) = '0'\r
+-- and (reg_disp_ptn_h(0) or reg_disp_ptn_l(0)) = '1') then\r
+-- reg_plt_addr <=\r
+-- "0" & reg_disp_attr(1 downto 0) & reg_disp_ptn_h(0) & reg_disp_ptn_l(0);\r
+-- elsif (conv_std_logic_vector(reg_nes_y, 9)(4) = '1'\r
+-- and (reg_disp_ptn_h(0) or reg_disp_ptn_l(0)) = '1') then\r
+-- reg_plt_addr <=\r
+-- "0" & reg_disp_attr(5 downto 4) & reg_disp_ptn_h(0) & reg_disp_ptn_l(0);\r
+-- else\r
+-- ---else: no output color >> universal bg color output.\r
+-- --0x3f00 is the universal bg palette.\r
+-- reg_plt_addr <= (others => '0');\r
+-- end if;\r
+-- end if;\r
+-- end if;--if (pi_rst_n = '0') then\r
+-- end process;\r
\r
rgb_out_p : process (pi_rst_n, pi_base_clk)\r
begin\r
if (reg_nes_x < HSCAN and reg_nes_y < VSCAN) then\r
--if or if not bg/sprite is shown, output color anyway \r
--sinse universal bg color is included..\r
- po_b <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (11 downto 8);\r
- po_g <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (7 downto 4);\r
- po_r <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (3 downto 0);\r
--- po_b <= "1100";\r
--- po_g <= "0011";\r
--- po_r <= "0101";\r
+-- po_b <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (11 downto 8);\r
+-- po_g <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (7 downto 4);\r
+-- po_r <= nes_color_palette(conv_integer(reg_plt_data(5 downto 0))) (3 downto 0);\r
+ po_b <= (others => '0');\r
+ po_g <= (others => '1');\r
+ po_r <= (others => '1');\r
else\r
po_b <= (others => '0');\r
po_g <= (others => '0');\r
po_spr_addr <= (others => 'Z');\r
\r
end rtl;\r
-\r