net: aquantia: replace AQ_HW_WAIT_FOR with readx_poll_timeout_atomic

David noticed the original define was hiding 'err' variable
reference. Thats confusing and counterintuitive.

Andrew noted the whole macro could be replaced with standard readx_poll
kernel macro. This makes code more readable.

Signed-off-by: Nikita Danilov <nikita.danilov@aquantia.com>
Signed-off-by: Igor Russkikh <igor.russkikh@aquantia.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
index dc88a12..bc71123 100644 (file)
--- a/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
+++ b/drivers/net/ethernet/aquantia/atlantic/aq_hw_utils.h
@@ -14,6 +14,8 @@
 #ifndef AQ_HW_UTILS_H
 #define AQ_HW_UTILS_H
 
+#include <linux/iopoll.h>
+
 #include "aq_common.h"
 
 #ifndef HIDWORD
@@ -23,18 +25,6 @@
 
 #define AQ_HW_SLEEP(_US_) mdelay(_US_)
 
-#define AQ_HW_WAIT_FOR(_B_, _US_, _N_) \
-do { \
-       unsigned int AQ_HW_WAIT_FOR_i; \
-       for (AQ_HW_WAIT_FOR_i = _N_; (!(_B_)) && (AQ_HW_WAIT_FOR_i);\
-       --AQ_HW_WAIT_FOR_i) {\
-               udelay(_US_); \
-       } \
-       if (!AQ_HW_WAIT_FOR_i) {\
-               err = -ETIME; \
-       } \
-} while (0)
-
 #define aq_pr_err(...) pr_err(AQ_CFG_DRV_NAME ": " __VA_ARGS__)
 #define aq_pr_trace(...) pr_info(AQ_CFG_DRV_NAME ": " __VA_ARGS__)
 

diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
index 30fdcb9..f6f8338 100644 (file)
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_a0.c
@@ -85,6 +85,7 @@ const struct aq_hw_caps_s hw_atl_a0_caps_aqc109 = {
 static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
 {
        int err = 0;
+       u32 val;
 
        hw_atl_glb_glb_reg_res_dis_set(self, 1U);
        hw_atl_pci_pci_reg_res_dis_set(self, 0U);
@@ -95,7 +96,9 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
        hw_atl_glb_soft_res_set(self, 1);
 
        /* check 10 times by 1ms */
-       AQ_HW_WAIT_FOR(hw_atl_glb_soft_res_get(self) == 0, 1000U, 10U);
+       err = readx_poll_timeout_atomic(hw_atl_glb_soft_res_get,
+                                       self, val, val == 0,
+                                       1000U, 10000U);
        if (err < 0)
                goto err_exit;
 
@@ -103,7 +106,9 @@ static int hw_atl_a0_hw_reset(struct aq_hw_s *self)
        hw_atl_itr_res_irq_set(self, 1U);
 
        /* check 10 times by 1ms */
-       AQ_HW_WAIT_FOR(hw_atl_itr_res_irq_get(self) == 0, 1000U, 10U);
+       err = readx_poll_timeout_atomic(hw_atl_itr_res_irq_get,
+                                       self, val, val == 0,
+                                       1000U, 10000U);
        if (err < 0)
                goto err_exit;
 
@@ -181,6 +186,7 @@ static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
        int err = 0;
        unsigned int i = 0U;
        unsigned int addr = 0U;
+       u32 val;
 
        for (i = 10, addr = 0U; i--; ++addr) {
                u32 key_data = cfg->is_rss ?
@@ -188,8 +194,9 @@ static int hw_atl_a0_hw_rss_hash_set(struct aq_hw_s *self,
                hw_atl_rpf_rss_key_wr_data_set(self, key_data);
                hw_atl_rpf_rss_key_addr_set(self, addr);
                hw_atl_rpf_rss_key_wr_en_set(self, 1U);
-               AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
-                              1000U, 10U);
+               err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get,
+                                               self, val, val == 0,
+                                               1000U, 10000U);
                if (err < 0)
                        goto err_exit;
        }
@@ -209,6 +216,7 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
        int err = 0;
        u16 bitary[1 + (HW_ATL_A0_RSS_REDIRECTION_MAX *
                   HW_ATL_A0_RSS_REDIRECTION_BITS / 16U)];
+       u32 val;
 
        memset(bitary, 0, sizeof(bitary));
 
@@ -222,8 +230,9 @@ static int hw_atl_a0_hw_rss_set(struct aq_hw_s *self,
                hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
                hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
                hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
-               AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
-                              1000U, 10U);
+               err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get,
+                                               self, val, val == 0,
+                                               1000U, 10000U);
                if (err < 0)
                        goto err_exit;
        }

diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
index c4cdc51..7eb5ea9 100644 (file)
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_b0.c
@@ -173,6 +173,7 @@ static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
        int err = 0;
        unsigned int i = 0U;
        unsigned int addr = 0U;
+       u32 val;
 
        for (i = 10, addr = 0U; i--; ++addr) {
                u32 key_data = cfg->is_rss ?
@@ -180,8 +181,9 @@ static int hw_atl_b0_hw_rss_hash_set(struct aq_hw_s *self,
                hw_atl_rpf_rss_key_wr_data_set(self, key_data);
                hw_atl_rpf_rss_key_addr_set(self, addr);
                hw_atl_rpf_rss_key_wr_en_set(self, 1U);
-               AQ_HW_WAIT_FOR(hw_atl_rpf_rss_key_wr_en_get(self) == 0,
-                              1000U, 10U);
+               err = readx_poll_timeout_atomic(hw_atl_rpf_rss_key_wr_en_get,
+                                               self, val, val == 0,
+                                               1000U, 10000U);
                if (err < 0)
                        goto err_exit;
        }
@@ -201,6 +203,7 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
        int err = 0;
        u16 bitary[1 + (HW_ATL_B0_RSS_REDIRECTION_MAX *
                   HW_ATL_B0_RSS_REDIRECTION_BITS / 16U)];
+       u32 val;
 
        memset(bitary, 0, sizeof(bitary));
 
@@ -214,8 +217,9 @@ static int hw_atl_b0_hw_rss_set(struct aq_hw_s *self,
                hw_atl_rpf_rss_redir_tbl_wr_data_set(self, bitary[i]);
                hw_atl_rpf_rss_redir_tbl_addr_set(self, i);
                hw_atl_rpf_rss_redir_wr_en_set(self, 1U);
-               AQ_HW_WAIT_FOR(hw_atl_rpf_rss_redir_wr_en_get(self) == 0,
-                              1000U, 10U);
+               err = readx_poll_timeout_atomic(hw_atl_rpf_rss_redir_wr_en_get,
+                                               self, val, val == 0,
+                                               1000U, 10000U);
                if (err < 0)
                        goto err_exit;
        }

diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
index 939f77e..f72194c 100644 (file)
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.c
@@ -1585,3 +1585,24 @@ void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
                                HW_ATL_RPF_L3_DSTA_ADR(location + i),
                                ipv6_dest[i]);
 }
+
+u32 hw_atl_sem_ram_get(struct aq_hw_s *self)
+{
+       return hw_atl_reg_glb_cpu_sem_get(self, HW_ATL_FW_SM_RAM);
+}
+
+u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp)
+{
+       return aq_hw_read_reg(aq_hw,
+                             HW_ATL_GLB_CPU_SCRATCH_SCP_ADR(scratch_scp));
+}
+
+u32 hw_atl_scrpad12_get(struct aq_hw_s *self)
+{
+       return  hw_atl_scrpad_get(self, 0xB);
+}
+
+u32 hw_atl_scrpad25_get(struct aq_hw_s *self)
+{
+       return hw_atl_scrpad_get(self, 0x18);
+}

diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
index 03c570d..40e6c1e 100644 (file)
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh.h
@@ -752,4 +752,16 @@ void hw_atl_rpfl3l4_ipv6_src_addr_set(struct aq_hw_s *aq_hw, u8 location,
 void hw_atl_rpfl3l4_ipv6_dest_addr_set(struct aq_hw_s *aq_hw, u8 location,
                                       u32 *ipv6_dest);
 
+/* get global microprocessor ram semaphore */
+u32 hw_atl_sem_ram_get(struct aq_hw_s *self);
+
+/* get global microprocessor scratch pad register */
+u32 hw_atl_scrpad_get(struct aq_hw_s *aq_hw, u32 scratch_scp);
+
+/* get global microprocessor scratch pad 12 register */
+u32 hw_atl_scrpad12_get(struct aq_hw_s *self);
+
+/* get global microprocessor scratch pad 25 register */
+u32 hw_atl_scrpad25_get(struct aq_hw_s *self);
+
 #endif /* HW_ATL_LLH_H */

diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
index 8470d92..50b4dee 100644 (file)
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_llh_internal.h
@@ -2519,4 +2519,6 @@
 /* Default value of bitfield l3_da0[1F:0] */
 #define HW_ATL_RPF_L3_DSTA_DEFAULT 0x0
 
+#define HW_ATL_FW_SM_RAM        0x2U
+
 #endif /* HW_ATL_LLH_INTERNAL_H */

diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
index 9b74a31..e5df40b 100644 (file)
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils.c
@@ -25,7 +25,9 @@
 #define HW_ATL_MIF_ADDR         0x0208U
 #define HW_ATL_MIF_VAL          0x020CU
 
-#define HW_ATL_FW_SM_RAM        0x2U
+#define HW_ATL_RPC_CONTROL_ADR  0x0338U
+#define HW_ATL_RPC_STATE_ADR    0x033CU
+
 #define HW_ATL_MPI_FW_VERSION  0x18
 #define HW_ATL_MPI_CONTROL_ADR  0x0368U
 #define HW_ATL_MPI_STATE_ADR    0x036CU
@@ -53,6 +55,12 @@ static int hw_atl_utils_ver_match(u32 ver_expected, u32 ver_actual);
 static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self,
                                      enum hal_atl_utils_fw_state_e state);
 
+static u32 hw_atl_utils_get_mpi_mbox_tid(struct aq_hw_s *self);
+static u32 hw_atl_utils_mpi_get_state(struct aq_hw_s *self);
+static u32 hw_atl_utils_mif_cmd_get(struct aq_hw_s *self);
+static u32 hw_atl_utils_mif_addr_get(struct aq_hw_s *self);
+static u32 hw_atl_utils_rpc_state_get(struct aq_hw_s *self);
+
 int hw_atl_utils_initfw(struct aq_hw_s *self, const struct aq_fw_ops **fw_ops)
 {
        int err = 0;
@@ -234,6 +242,7 @@ int hw_atl_utils_soft_reset(struct aq_hw_s *self)
 {
        int k;
        u32 boot_exit_code = 0;
+       u32 val;
 
        for (k = 0; k < 1000; ++k) {
                u32 flb_status = aq_hw_read_reg(self,
@@ -260,9 +269,11 @@ int hw_atl_utils_soft_reset(struct aq_hw_s *self)
                int err = 0;
 
                hw_atl_utils_mpi_set_state(self, MPI_DEINIT);
-               AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR) &
-                               HW_ATL_MPI_STATE_MSK) == MPI_DEINIT,
-                              10, 1000U);
+               err = readx_poll_timeout_atomic(hw_atl_utils_mpi_get_state,
+                                               self, val,
+                                               (val & HW_ATL_MPI_STATE_MSK) ==
+                                                MPI_DEINIT,
+                                               10, 10000U);
                if (err)
                        return err;
        }
@@ -277,10 +288,11 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
                                  u32 *p, u32 cnt)
 {
        int err = 0;
+       u32 val;
 
-       AQ_HW_WAIT_FOR(hw_atl_reg_glb_cpu_sem_get(self,
-                                                 HW_ATL_FW_SM_RAM) == 1U,
-                      1U, 10000U);
+       err = readx_poll_timeout_atomic(hw_atl_sem_ram_get,
+                                       self, val, val == 1U,
+                                       1U, 10000U);
 
        if (err < 0) {
                bool is_locked;
@@ -299,13 +311,14 @@ int hw_atl_utils_fw_downld_dwords(struct aq_hw_s *self, u32 a,
                aq_hw_write_reg(self, HW_ATL_MIF_CMD, 0x00008000U);
 
                if (IS_CHIP_FEATURE(REVISION_B1))
-                       AQ_HW_WAIT_FOR(a != aq_hw_read_reg(self,
-                                                          HW_ATL_MIF_ADDR),
-                                      1, 1000U);
+                       err = readx_poll_timeout_atomic(hw_atl_utils_mif_addr_get,
+                                                       self, val, val != a,
+                                                       1U, 1000U);
                else
-                       AQ_HW_WAIT_FOR(!(0x100 & aq_hw_read_reg(self,
-                                                          HW_ATL_MIF_CMD)),
-                                      1, 1000U);
+                       err = readx_poll_timeout_atomic(hw_atl_utils_mif_cmd_get,
+                                                       self, val,
+                                                       !(val & 0x100),
+                                                       1U, 1000U);
 
                *(p++) = aq_hw_read_reg(self, HW_ATL_MIF_VAL);
                a += 4;
@@ -320,6 +333,7 @@ err_exit:
 static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
                                         u32 cnt)
 {
+       u32 val;
        int err = 0;
        bool is_locked;
 
@@ -337,10 +351,11 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
                                        (0x80000000 | (0xFFFF & (offset * 4))));
                        hw_atl_mcp_up_force_intr_set(self, 1);
                        /* 1000 times by 10us = 10ms */
-                       AQ_HW_WAIT_FOR((aq_hw_read_reg(self,
-                                                      0x32C) & 0xF0000000) !=
-                                      0x80000000,
-                                      10, 1000);
+                       err = readx_poll_timeout_atomic(hw_atl_scrpad12_get,
+                                                       self, val,
+                                                       (val & 0xF0000000) ==
+                                                        0x80000000,
+                                                       10U, 10000U);
                }
        } else {
                u32 offset = 0;
@@ -351,8 +366,10 @@ static int hw_atl_utils_fw_upload_dwords(struct aq_hw_s *self, u32 a, u32 *p,
                        aq_hw_write_reg(self, 0x20C, p[offset]);
                        aq_hw_write_reg(self, 0x200, 0xC000);
 
-                       AQ_HW_WAIT_FOR((aq_hw_read_reg(self, 0x200U) &
-                                       0x100) == 0, 10, 1000);
+                       err = readx_poll_timeout_atomic(hw_atl_utils_mif_cmd_get,
+                                                       self, val,
+                                                       (val & 0x100) == 0,
+                                                       1000U, 10000U);
                }
        }
 
@@ -395,15 +412,14 @@ static int hw_atl_utils_init_ucp(struct aq_hw_s *self,
        hw_atl_reg_glb_cpu_scratch_scp_set(self, 0x00000000U, 25U);
 
        /* check 10 times by 1ms */
-       AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
-                             aq_hw_read_reg(self, 0x360U)), 1000U, 10U);
+       err = readx_poll_timeout_atomic(hw_atl_scrpad25_get,
+                                       self, self->mbox_addr,
+                                       self->mbox_addr != 0U,
+                                       1000U, 10000U);
 
        return err;
 }
 
-#define HW_ATL_RPC_CONTROL_ADR 0x0338U
-#define HW_ATL_RPC_STATE_ADR   0x033CU
-
 struct aq_hw_atl_utils_fw_rpc_tid_s {
        union {
                u32 val;
@@ -452,10 +468,10 @@ int hw_atl_utils_fw_rpc_wait(struct aq_hw_s *self,
 
                self->rpc_tid = sw.tid;
 
-               AQ_HW_WAIT_FOR(sw.tid ==
-                              (fw.val =
-                               aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR),
-                               fw.tid), 1000U, 100U);
+               err = readx_poll_timeout_atomic(hw_atl_utils_rpc_state_get,
+                                               self, fw.val,
+                                               sw.tid == fw.tid,
+                                               1000U, 100000U);
 
                if (fw.len == 0xFFFFU) {
                        err = hw_atl_utils_fw_rpc_call(self, sw.len);
@@ -559,10 +575,11 @@ static int hw_atl_utils_mpi_set_state(struct aq_hw_s *self,
 
                transaction_id = mbox.transaction_id;
 
-               AQ_HW_WAIT_FOR(transaction_id !=
-                              (hw_atl_utils_mpi_read_mbox(self, &mbox),
-                               mbox.transaction_id),
-                              1000U, 100U);
+               err = readx_poll_timeout_atomic(hw_atl_utils_get_mpi_mbox_tid,
+                                               self, mbox.transaction_id,
+                                               transaction_id !=
+                                               mbox.transaction_id,
+                                               1000U, 100000U);
                if (err < 0)
                        goto err_exit;
        }
@@ -905,6 +922,35 @@ err_exit:
        return err;
 }
 
+static u32 hw_atl_utils_get_mpi_mbox_tid(struct aq_hw_s *self)
+{
+       struct hw_atl_utils_mbox_header mbox;
+
+       hw_atl_utils_mpi_read_mbox(self, &mbox);
+
+       return mbox.transaction_id;
+}
+
+static u32 hw_atl_utils_mpi_get_state(struct aq_hw_s *self)
+{
+       return aq_hw_read_reg(self, HW_ATL_MPI_STATE_ADR);
+}
+
+static u32 hw_atl_utils_mif_cmd_get(struct aq_hw_s *self)
+{
+       return aq_hw_read_reg(self, HW_ATL_MIF_CMD);
+}
+
+static u32 hw_atl_utils_mif_addr_get(struct aq_hw_s *self)
+{
+       return aq_hw_read_reg(self, HW_ATL_MIF_ADDR);
+}
+
+static u32 hw_atl_utils_rpc_state_get(struct aq_hw_s *self)
+{
+       return aq_hw_read_reg(self, HW_ATL_RPC_STATE_ADR);
+}
+
 const struct aq_fw_ops aq_fw_1x_ops = {
        .init = hw_atl_utils_mpi_create,
        .deinit = hw_atl_fw1x_deinit,

diff --git a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c
index 7de3220..c628290 100644 (file)
--- a/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c
+++ b/drivers/net/ethernet/aquantia/atlantic/hw_atl/hw_atl_utils_fw2x.c
@@ -20,15 +20,14 @@
 #include "hw_atl_utils.h"
 #include "hw_atl_llh.h"
 
-#define HW_ATL_FW2X_MPI_EFUSE_ADDR     0x364
-#define HW_ATL_FW2X_MPI_MBOX_ADDR      0x360
 #define HW_ATL_FW2X_MPI_RPC_ADDR        0x334
 
+#define HW_ATL_FW2X_MPI_MBOX_ADDR       0x360
+#define HW_ATL_FW2X_MPI_EFUSE_ADDR     0x364
 #define HW_ATL_FW2X_MPI_CONTROL_ADDR   0x368
 #define HW_ATL_FW2X_MPI_CONTROL2_ADDR  0x36C
-
 #define HW_ATL_FW2X_MPI_STATE_ADDR     0x370
-#define HW_ATL_FW2X_MPI_STATE2_ADDR    0x374
+#define HW_ATL_FW2X_MPI_STATE2_ADDR     0x374
 
 #define HW_ATL_FW2X_CAP_PAUSE            BIT(CAPS_HI_PAUSE)
 #define HW_ATL_FW2X_CAP_ASYM_PAUSE       BIT(CAPS_HI_ASYMMETRIC_PAUSE)
@@ -72,17 +71,24 @@ static int aq_fw2x_set_link_speed(struct aq_hw_s *self, u32 speed);
 static int aq_fw2x_set_state(struct aq_hw_s *self,
                             enum hal_atl_utils_fw_state_e state);
 
+static u32 aq_fw2x_mbox_get(struct aq_hw_s *self);
+static u32 aq_fw2x_rpc_get(struct aq_hw_s *self);
+static u32 aq_fw2x_state2_get(struct aq_hw_s *self);
+
 static int aq_fw2x_init(struct aq_hw_s *self)
 {
        int err = 0;
 
        /* check 10 times by 1ms */
-       AQ_HW_WAIT_FOR(0U != (self->mbox_addr =
-                      aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR)),
-                      1000U, 10U);
-       AQ_HW_WAIT_FOR(0U != (self->rpc_addr =
-                      aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR)),
-                      1000U, 100U);
+       err = readx_poll_timeout_atomic(aq_fw2x_mbox_get,
+                                       self, self->mbox_addr,
+                                       self->mbox_addr != 0U,
+                                       1000U, 10000U);
+
+       err = readx_poll_timeout_atomic(aq_fw2x_rpc_get,
+                                       self, self->rpc_addr,
+                                       self->rpc_addr != 0U,
+                                       1000U, 100000U);
 
        return err;
 }
@@ -286,16 +292,18 @@ static int aq_fw2x_update_stats(struct aq_hw_s *self)
        int err = 0;
        u32 mpi_opts = aq_hw_read_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR);
        u32 orig_stats_val = mpi_opts & BIT(CAPS_HI_STATISTICS);
+       u32 stats_val;
 
        /* Toggle statistics bit for FW to update */
        mpi_opts = mpi_opts ^ BIT(CAPS_HI_STATISTICS);
        aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 
        /* Wait FW to report back */
-       AQ_HW_WAIT_FOR(orig_stats_val !=
-                      (aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
-                       BIT(CAPS_HI_STATISTICS)),
-                      1U, 10000U);
+       err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
+                                       self, stats_val,
+                                       orig_stats_val != (stats_val &
+                                       BIT(CAPS_HI_STATISTICS)),
+                                       1U, 10000U);
        if (err)
                return err;
 
@@ -309,6 +317,7 @@ static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
        unsigned int rpc_size = 0U;
        u32 mpi_opts;
        int err = 0;
+       u32 val;
 
        rpc_size = sizeof(rpc->msg_id) + sizeof(*cfg);
 
@@ -337,8 +346,10 @@ static int aq_fw2x_set_sleep_proxy(struct aq_hw_s *self, u8 *mac)
        mpi_opts |= HW_ATL_FW2X_CTRL_SLEEP_PROXY;
        aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 
-       AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
-                       HW_ATL_FW2X_CTRL_SLEEP_PROXY), 1U, 10000U);
+       err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
+                                       self, val,
+                                       val & HW_ATL_FW2X_CTRL_SLEEP_PROXY,
+                                       1U, 10000U);
 
 err_exit:
        return err;
@@ -350,6 +361,7 @@ static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
        struct fw2x_msg_wol *msg = NULL;
        u32 mpi_opts;
        int err = 0;
+       u32 val;
 
        err = hw_atl_utils_fw_rpc_wait(self, &rpc);
        if (err < 0)
@@ -374,8 +386,9 @@ static int aq_fw2x_set_wol_params(struct aq_hw_s *self, u8 *mac)
        mpi_opts |= HW_ATL_FW2X_CTRL_WOL;
        aq_hw_write_reg(self, HW_ATL_FW2X_MPI_CONTROL2_ADDR, mpi_opts);
 
-       AQ_HW_WAIT_FOR((aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR) &
-                       HW_ATL_FW2X_CTRL_WOL), 1U, 10000U);
+       err = readx_poll_timeout_atomic(aq_fw2x_state2_get,
+                                       self, val, val & HW_ATL_FW2X_CTRL_WOL,
+                                       1U, 10000U);
 
 err_exit:
        return err;
@@ -471,6 +484,21 @@ static u32 aq_fw2x_get_flow_control(struct aq_hw_s *self, u32 *fcmode)
        return 0;
 }
 
+static u32 aq_fw2x_mbox_get(struct aq_hw_s *self)
+{
+       return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_MBOX_ADDR);
+}
+
+static u32 aq_fw2x_rpc_get(struct aq_hw_s *self)
+{
+       return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_RPC_ADDR);
+}
+
+static u32 aq_fw2x_state2_get(struct aq_hw_s *self)
+{
+       return aq_hw_read_reg(self, HW_ATL_FW2X_MPI_STATE2_ADDR);
+}
+
 const struct aq_fw_ops aq_fw_2x_ops = {
        .init = aq_fw2x_init,
        .deinit = aq_fw2x_deinit,