GlobalISel: move vector extract/insert inside generic opcode region.

Otherwise they won't be legalized or selected, causing instruction selection to
fail horribly.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297666 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/Target/TargetOpcodes.def b/include/llvm/Target/TargetOpcodes.def
index e3ae2fa..d5195c6 100644 (file)
--- a/include/llvm/Target/TargetOpcodes.def
+++ b/include/llvm/Target/TargetOpcodes.def
@@ -392,15 +392,17 @@ HANDLE_TARGET_OPCODE(G_GEP)
 /// *down* to the given alignment.
 HANDLE_TARGET_OPCODE(G_PTR_MASK)
 
-/// Generic BRANCH instruction. This is an unconditional branch.
-HANDLE_TARGET_OPCODE(G_BR)
-
 /// Generic insertelement.
 HANDLE_TARGET_OPCODE(G_INSERT_VECTOR_ELT)
 
 /// Generic extractelement.
 HANDLE_TARGET_OPCODE(G_EXTRACT_VECTOR_ELT)
 
+/// Generic BRANCH instruction. This is an unconditional branch.
+HANDLE_TARGET_OPCODE(G_BR)
+// WARNING: make sure you update the PRE_ISEL_GENERIC_OPCODE_END if you put
+// anything after G_BR!!! Better yet, don't.
+
 // TODO: Add more generic opcodes as we move along.
 
 /// Marker for the end of the generic opcode.

diff --git a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
index 087faa2..d4d05f6 100644 (file)
--- a/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
+++ b/test/CodeGen/AArch64/GlobalISel/arm64-fallback.ll
@@ -138,3 +138,12 @@ broken:
 continue:
   ret void
 }
+
+; FALLBACK-WITH-REPORT-ERR: remark: <unknown>:0:0: unable to legalize instruction: {{.*}} G_EXTRACT_VECTOR
+; FALLBACK-WITH-REPORT-ERR: warning: Instruction selection used fallback path for unhandled_extract
+; FALLBACK-WITH-REPORT-OUT-LABEL: unhandled_extract:
+define i32 @unhandled_extract(<2 x i32> %in, i64 %elt) {
+  %tmp = extractelement <2 x i32> %in, i64 %elt
+  %res = add i32 %tmp, 1
+  ret i32 %res
+}