author | Feifei Xu <Feifei.Xu@amd.com> | |
Mon, 27 Nov 2017 09:32:44 +0000 (17:32 +0800) | ||
committer | Alex Deucher <alexander.deucher@amd.com> | |
Wed, 6 Dec 2017 17:48:26 +0000 (12:48 -0500) |
drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_default.h | [moved from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_default.h with 100% similarity] | patch | blob | history |
drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_offset.h | [moved from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_offset.h with 100% similarity] | patch | blob | history |
drivers/gpu/drm/amd/include/asic_reg/thm/thm_10_0_sh_mask.h | [moved from drivers/gpu/drm/amd/include/asic_reg/raven1/THM/thm_10_0_sh_mask.h with 100% similarity] | patch | blob | history |
drivers/gpu/drm/amd/powerplay/hwmgr/rv_inc.h | patch | blob | history |