apu code integrated, but regression test doesn't work...

diff --git a/de1_nes/apu/apu.vhd b/de1_nes/apu/apu.vhd
index 55d9bc8..ffe87f3 100644 (file)
--- a/de1_nes/apu/apu.vhd
+++ b/de1_nes/apu/apu.vhd
@@ -100,30 +100,37 @@ begin
     --apu register access process
     reg_set_p : process (rst_n, ce_n, r_nw, cpu_addr, cpu_d)
     begin
-        if (rst_n = '1' and ce_n = '0') then
-            if (r_nw = '0') then
-                --apu write
-                cpu_d <= (others => 'Z');
-                if (cpu_addr(4 downto 0) = OAM_DMA) then
-                    dma_start_n <= '0';
-                else
-                    dma_start_n <= '1';
-                end if;
-            elsif (r_nw = '1') then
-                --apu read
-                if (cpu_addr(4 downto 0) = OAM_JP1) then
-                    cpu_d <= (others => '0');
-                elsif (cpu_addr(4 downto 0) = OAM_JP2) then
-                    cpu_d <= (others => '0');
-                else
-                    --return dummy zero vale.
-                    cpu_d <= (others => '0');
-                end if;
-            end if;
-        else
-            cpu_d <= (others => 'Z');
+        if (rst_n = '0') then
+--            cpu_d <= (others => 'Z');
             dma_start_n <= '1';
-        end if; --if (rst_n = '1' and ce_n = '0') 
+        elsif (rising_edge(clk)) then
+--            if (ce_n = '0') then
+--                if (r_nw = '0') then
+--                    --apu write
+--                    cpu_d <= (others => 'Z');
+--                    if (cpu_addr(4 downto 0) = OAM_DMA) then
+--                        dma_start_n <= '0';
+--                    else
+--                        dma_start_n <= '1';
+--                    end if;
+--                elsif (r_nw = '1') then
+--                    dma_start_n <= '1';
+--                    
+--                    --joy pad read
+--                    if (cpu_addr(4 downto 0) = OAM_JP1) then
+--                        cpu_d <= (others => '0');
+--                    elsif (cpu_addr(4 downto 0) = OAM_JP2) then
+--                        cpu_d <= (others => '0');
+--                    else
+--                        --return dummy zero vale.
+--                        cpu_d <= (others => '0');
+--                    end if;
+--                end if;
+--            else
+--                cpu_d <= (others => 'Z');
+--                dma_start_n <= '1';
+--            end if; --if (ce_n = '0') 
+        end if; --if (rst_n = '0') then
     end process;
 
     --dma operation process
@@ -131,62 +138,66 @@ begin
     begin
         if (rst_n = '0') then
             dma_next_status <= DMA_ST_IDLE;
+            dma_status_we_n <= '1';
             dma_end_n <= '1';
-            rdy <= '1';
             dma_process_n <= '1';
             cpu_addr <= (others => 'Z');
             cpu_d <= (others => 'Z');
             r_nw <= 'Z';
-        else
-            if (clk'event and clk = '0') then
-                if (dma_start_n = '0') then
-                    --pull rdy pin down to stop cpu bus accessing.
-                    rdy <= '0';
-                end if;
-                if (dma_end_n = '0') then
-                    --pull rdy pin up to re-enable cpu bus accessing.
-                    rdy <= '1';
-                end if;
-            end if;
-
-            if (clk'event and clk = '1') then
-                if (dma_status = DMA_ST_IDLE) then
-                    if (dma_start_n = '0') then
-                        dma_status_we_n <= '0';
-                        dma_next_status <= DMA_ST_SETUP;
-                    end if;
-                    dma_process_n <= '1';
-                    dma_end_n <= '1';
-                    cpu_addr <= (others => 'Z');
-                    cpu_d <= (others => 'Z');
-                    r_nw <= 'Z';
-                elsif (dma_status = DMA_ST_SETUP) then
-                    cpu_addr <= OAMADDR;
-                    cpu_d <= (others => '0');
-                    r_nw <= '0';
-                    dma_next_status <= DMA_ST_PROCESS;
-                elsif (dma_status = DMA_ST_PROCESS) then
-                    if (dma_addr(dsize - 1 downto 0) = "11111111" and dma_cnt_ce_n(0) = '1') then
-                        dma_status_we_n <= '0';
-                        dma_next_status <= DMA_ST_IDLE;
-                        dma_end_n <= '0';
-                    else
-                        dma_status_we_n <= '1';
-                        dma_process_n <= '0';
-                        dma_end_n <= '1';
-                    end if;
-
-                    if (dma_cnt_ce_n(0) = '0') then
-                        r_nw <= '1';
-                        cpu_addr <= dma_addr;
-                        cpu_d <= (others => 'Z');
-                    elsif (dma_cnt_ce_n(0) = '1') then
-                        r_nw <= '0';
-                        cpu_addr <= OAMDATA;
-                        cpu_d <= oam_data;
-                    end if;
-                end if;--if (dma_status = DMA_ST_IDLE) then
-            end if;--if (clk'event and clk = '1') then
+        elsif (rising_edge(clk)) then
+--            if (dma_status = DMA_ST_IDLE) then
+--                if (dma_start_n = '0') then
+--                    dma_status_we_n <= '0';
+--                    dma_next_status <= DMA_ST_SETUP;
+--                end if;
+--                dma_process_n <= '1';
+--                dma_end_n <= '1';
+--                cpu_addr <= (others => 'Z');
+--                cpu_d <= (others => 'Z');
+--                r_nw <= 'Z';
+--            elsif (dma_status = DMA_ST_SETUP) then
+--                cpu_addr <= OAMADDR;
+--                cpu_d <= (others => '0');
+--                r_nw <= '0';
+--                dma_next_status <= DMA_ST_PROCESS;
+--            elsif (dma_status = DMA_ST_PROCESS) then
+--                if (dma_addr(dsize - 1 downto 0) = "11111111" and dma_cnt_ce_n(0) = '1') then
+--                    dma_status_we_n <= '0';
+--                    dma_next_status <= DMA_ST_IDLE;
+--                    dma_end_n <= '0';
+--                else
+--                    dma_status_we_n <= '1';
+--                    dma_process_n <= '0';
+--                    dma_end_n <= '1';
+--                end if;
+--
+--                if (dma_cnt_ce_n(0) = '0') then
+--                    r_nw <= '1';
+--                    cpu_addr <= dma_addr;
+--                    cpu_d <= (others => 'Z');
+--                elsif (dma_cnt_ce_n(0) = '1') then
+--                    r_nw <= '0';
+--                    cpu_addr <= OAMDATA;
+--                    cpu_d <= oam_data;
+--                end if;
+--            end if;--if (dma_status = DMA_ST_IDLE) then
+        end if;--if (rst_n = '0') then
+    end process;
+
+    rdy_p : process (rst_n, clk_n)
+    begin
+        if (rst_n = '0') then
+            rdy <= '1';
+        elsif (rising_edge(clk_n)) then
+--            if (dma_start_n = '0') then
+--                --pull rdy pin down to stop cpu bus accessing.
+--                rdy <= '0';
+--            elsif (dma_end_n = '0') then
+--                --pull rdy pin up to re-enable cpu bus accessing.
+--                rdy <= '1';
+--            else
+--                rdy <= '1';
+--            end if;
         end if;
     end process;
 

diff --git a/de1_nes/de1_nes.qsf b/de1_nes/de1_nes.qsf
index 14051ca..3080fba 100644 (file)
--- a/de1_nes/de1_nes.qsf
+++ b/de1_nes/de1_nes.qsf
@@ -110,13 +110,13 @@ set_location_assignment PIN_M5 -to dram_udqm
 set_location_assignment PIN_R8 -to dram_we_n\r
 \r
 #project files\r
-set_global_assignment -name VHDL_FILE apu/apu.vhd\r
 set_global_assignment -name VHDL_FILE address_decoder.vhd\r
 set_global_assignment -name VHDL_FILE motonesfpga_common.vhd\r
 set_global_assignment -name VHDL_FILE clock/clock_divider.vhd\r
 set_global_assignment -name VHDL_FILE mem/prg_rom.vhd\r
 set_global_assignment -name VHDL_FILE mem/chr_rom.vhd\r
 set_global_assignment -name VHDL_FILE mem/ram.vhd\r
+set_global_assignment -name VHDL_FILE apu/apu.vhd\r
 set_global_assignment -name VHDL_FILE ppu/ppu_registers.vhd\r
 set_global_assignment -name VHDL_FILE ppu/vga_ppu.vhd\r
 set_global_assignment -name VHDL_FILE ppu/ppu.vhd\r

diff --git a/de1_nes/de1_nes.vhd b/de1_nes/de1_nes.vhd
index 0dae18a..d50cc08 100644 (file)
--- a/de1_nes/de1_nes.vhd
+++ b/de1_nes/de1_nes.vhd
@@ -341,7 +341,7 @@ begin
     dbg_stat_we_n    ,
     dbg_idl_h, dbg_idl_l, dbg_dbb_r, dbg_dbb_w,
 
-                cpu_clk, '1', --rdy, -----for testing...
+                cpu_clk, rdy,
                 rst_n, irq_n, nmi_n, dbe, r_nw, 
                 phi1, phi2, addr, d_io);
 
@@ -474,9 +474,9 @@ begin
     vram_nt1 : ram generic map (vram_1k, data_size)
             port map (mem_clk, nt1_ce_n, rd_n, wr_n, v_addr(vram_1k - 1 downto 0), vram_ad);
 
---    --APU/DMA instance
---    apu_inst : apu
---        port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);
+    --APU/DMA instance
+    apu_inst : apu
+        port map (cpu_clk, apu_ce_n, rst_n, r_nw, addr, d_io, rdy);
 
 end rtl;
 

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
index 9ffef8d..d767dfe 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_gate_vhdl.do
@@ -16,7 +16,7 @@ vsim -t 1ps +transport_int_delays +transport_path_delays -sdftyp /sim_board=de1_
 \r
 add wave -divider cpu\r
 add wave -label rst_n       sim:/testbench_motones_sim/sim_board/rst_n\r
-add wave -label nmi_input   sim:/testbench_motones_sim/sim_board/dummy_nmi\r
+add wave -label nmi         sim:/testbench_motones_sim/sim_board/dbg_nmi\r
 add wave -label cpu_clk       sim:/testbench_motones_sim/sim_board/dbg_cpu_clk\r
 #add wave -label vga_clk   sim:/testbench_motones_sim/sim_board/dbg_ppu_scrl_x(4)\r
 #add wave -label mem_clk sim:/testbench_motones_sim/sim_board/dbg_mem_clk\r

diff --git a/de1_nes/testbench_motones_sim.vhd b/de1_nes/testbench_motones_sim.vhd
index 2e015b7..67529a3 100644 (file)
--- a/de1_nes/testbench_motones_sim.vhd
+++ b/de1_nes/testbench_motones_sim.vhd
@@ -42,7 +42,7 @@ architecture stimulus of testbench_motones_sim is
     signal dbg_ppu_data, dbg_ppu_scrl_x, dbg_ppu_scrl_y : out std_logic_vector (7 downto 0);
     signal dbg_disp_nt, dbg_disp_attr : out std_logic_vector (7 downto 0);
     signal dbg_disp_ptn_h, dbg_disp_ptn_l : out std_logic_vector (15 downto 0);
-    signal dummy_nmi  : in std_logic;
+    signal dbg_nmi  : out std_logic;
     
     
 --NES instance
@@ -61,6 +61,7 @@ architecture stimulus of testbench_motones_sim is
     signal base_clk         : std_logic;
     signal reset_input      : std_logic;
     signal nmi_input      : std_logic;
+    signal dbg_nmi      : std_logic;
 
     signal h_sync_n    : std_logic;
     signal v_sync_n    : std_logic;
@@ -145,7 +146,7 @@ dbg_disp_nt, dbg_disp_attr ,
 dbg_disp_ptn_h, dbg_disp_ptn_l ,
 --dbg_ppu_addr_we_n,
 --dbg_ppu_clk_cnt          ,
-nmi_input,
+dbg_nmi,
     
     base_clk, reset_input, joypad1, joypad2, 
             h_sync_n, v_sync_n, r, g, b);

diff --git a/tools/regression-test/regression.asm b/tools/regression-test/regression.asm
index f61a92b..c509bc7 100644 (file)
--- a/tools/regression-test/regression.asm
+++ b/tools/regression-test/regression.asm
@@ -59,6 +59,9 @@
     jsr status_test\r
     jsr ppu_test\r
 \r
+    ;;this function doesn't work.. must investigate!!!!\r
+;    jsr dma_test\r
+\r
 .endproc\r
 \r
 \r
@@ -125,6 +128,55 @@ mainloop:
        jmp     mainloop\r
 \r
 \r
+.proc dma_test\r
+    ;;dma test data.\r
+    ldy #$00\r
+    ldx #$41\r
+    stx $00\r
+    ldx #$00\r
+dma_set:\r
+    ;;y pos\r
+    txa\r
+    sta $0200, y\r
+    iny\r
+    ;;tile index\r
+    lda $00\r
+    cmp #$5b\r
+    bne inc_tile\r
+    lda #$41\r
+    sta $00\r
+inc_tile:\r
+    inc $00\r
+    sta $0200, y\r
+    iny\r
+    ;;attribute\r
+    lda #$01\r
+    sta $0200, y\r
+    iny\r
+    ;;x pos\r
+    txa\r
+    adc #$03\r
+    tax\r
+    rol\r
+    sta $0200, y\r
+    iny\r
+    bne dma_set\r
+\r
+    ;;dma start.\r
+    lda #$02\r
+    sta $4014\r
+\r
+    jsr check_ppu\r
+    lda ad_dma_test\r
+    sta $00\r
+    lda ad_dma_test+1\r
+    sta $01\r
+    jsr print_ln\r
+\r
+    rts\r
+.endproc\r
+\r
+\r
 nmi_test:\r
     jsr update_counter\r
     jsr update_scroll\r
@@ -2346,6 +2398,12 @@ ad_status_test:
     .byte   "status test..."\r
     .byte   $00\r
 \r
+ad_dma_test:\r
+    .addr   :+\r
+:\r
+    .byte   "dma test..."\r
+    .byte   $00\r
+\r
 ad_ppu_test:\r
     .addr   :+\r
 :\r