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drm/tegra: dp: Read channel coding capability from sink
authorThierry Reding <treding@nvidia.com>
Mon, 5 Feb 2018 13:07:57 +0000 (14:07 +0100)
committerThierry Reding <treding@nvidia.com>
Mon, 28 Oct 2019 10:18:45 +0000 (11:18 +0100)
Parse from the sink capabilities whether or not it supports ANSI 8B/10B
channel coding as specified in ANSI X3.230-1994, clause 11.

Signed-off-by: Thierry Reding <treding@nvidia.com>
drivers/gpu/drm/tegra/dp.c
drivers/gpu/drm/tegra/dp.h

index e22ebab..0bd87cf 100644 (file)
@@ -13,6 +13,7 @@ static void drm_dp_link_caps_reset(struct drm_dp_link_caps *caps)
        caps->enhanced_framing = false;
        caps->tps3_supported = false;
        caps->fast_training = false;
+       caps->channel_coding = false;
 }
 
 void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
@@ -21,6 +22,7 @@ void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
        dest->enhanced_framing = src->enhanced_framing;
        dest->tps3_supported = src->tps3_supported;
        dest->fast_training = src->fast_training;
+       dest->channel_coding = src->channel_coding;
 }
 
 static void drm_dp_link_reset(struct drm_dp_link *link)
@@ -67,6 +69,7 @@ int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link)
        link->caps.enhanced_framing = drm_dp_enhanced_frame_cap(dpcd);
        link->caps.tps3_supported = drm_dp_tps3_supported(dpcd);
        link->caps.fast_training = drm_dp_fast_training_cap(dpcd);
+       link->caps.channel_coding = drm_dp_channel_coding_supported(dpcd);
 
        link->rate = link->max_rate;
        link->lanes = link->max_lanes;
index 9990788..984dac2 100644 (file)
@@ -35,6 +35,13 @@ struct drm_dp_link_caps {
         * AUX CH handshake not required for link training
         */
        bool fast_training;
+
+       /**
+        * @channel_coding:
+        *
+        * ANSI 8B/10B channel coding capability
+        */
+       bool channel_coding;
 };
 
 void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,