amdgpu: Prepare DCN floating point macros for generic arch support

Introduce DC_FP_START()/DC_FP_END() macros to help enable floating
point kernel mode support across various architectures.

v2: move copyright update to commit which adds the changes

Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
index a4ddd65..5dc8ffe 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
@@ -622,7 +622,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
 {
        bool updated = false;
 
-       kernel_fpu_begin();
+       DC_FP_START();
        if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
                        && dc->debug.sr_exit_time_ns) {
                updated = true;
@@ -658,7 +658,7 @@ static bool dcn_bw_apply_registry_override(struct dc *dc)
                dc->dcn_soc->dram_clock_change_latency =
                                dc->debug.dram_clock_change_latency_ns / 1000.0;
        }
-       kernel_fpu_end();
+       DC_FP_END();
 
        return updated;
 }
@@ -738,7 +738,7 @@ bool dcn_validate_bandwidth(
                dcn_bw_sync_calcs_and_dml(dc);
 
        memset(v, 0, sizeof(*v));
-       kernel_fpu_begin();
+       DC_FP_START();
 
        v->sr_exit_time = dc->dcn_soc->sr_exit_time;
        v->sr_enter_plus_exit_time = dc->dcn_soc->sr_enter_plus_exit_time;
@@ -1271,7 +1271,7 @@ bool dcn_validate_bandwidth(
        bw_limit = dc->dcn_soc->percent_disp_bw_limit * v->fabric_and_dram_bandwidth_vmax0p9;
        bw_limit_pass = (v->total_data_read_bandwidth / 1000.0) < bw_limit;
 
-       kernel_fpu_end();
+       DC_FP_END();
 
        PERFORMANCE_TRACE_END();
        BW_VAL_TRACE_FINISH();
@@ -1439,7 +1439,7 @@ void dcn_bw_update_from_pplib(struct dc *dc)
        res = dm_pp_get_clock_levels_by_type_with_voltage(
                        ctx, DM_PP_CLOCK_TYPE_FCLK, &fclks);
 
-       kernel_fpu_begin();
+       DC_FP_START();
 
        if (res)
                res = verify_clock_values(&fclks);
@@ -1459,12 +1459,12 @@ void dcn_bw_update_from_pplib(struct dc *dc)
        } else
                BREAK_TO_DEBUGGER();
 
-       kernel_fpu_end();
+       DC_FP_END();
 
        res = dm_pp_get_clock_levels_by_type_with_voltage(
                        ctx, DM_PP_CLOCK_TYPE_DCFCLK, &dcfclks);
 
-       kernel_fpu_begin();
+       DC_FP_START();
 
        if (res)
                res = verify_clock_values(&dcfclks);
@@ -1477,7 +1477,7 @@ void dcn_bw_update_from_pplib(struct dc *dc)
        } else
                BREAK_TO_DEBUGGER();
 
-       kernel_fpu_end();
+       DC_FP_END();
 }
 
 void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
@@ -1492,11 +1492,11 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
        if (!pp || !pp->set_wm_ranges)
                return;
 
-       kernel_fpu_begin();
+       DC_FP_START();
        min_fclk_khz = dc->dcn_soc->fabric_and_dram_bandwidth_vmin0p65 * 1000000 / 32;
        min_dcfclk_khz = dc->dcn_soc->dcfclkv_min0p65 * 1000;
        socclk_khz = dc->dcn_soc->socclk * 1000;
-       kernel_fpu_end();
+       DC_FP_END();
 
        /* Now notify PPLib/SMU about which Watermarks sets they should select
         * depending on DPM state they are in. And update BW MGR GFX Engine and
@@ -1547,7 +1547,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
 
 void dcn_bw_sync_calcs_and_dml(struct dc *dc)
 {
-       kernel_fpu_begin();
+       DC_FP_START();
        DC_LOG_BANDWIDTH_CALCS("sr_exit_time: %f ns\n"
                        "sr_enter_plus_exit_time: %f ns\n"
                        "urgent_latency: %f ns\n"
@@ -1736,5 +1736,5 @@ void dcn_bw_sync_calcs_and_dml(struct dc *dc)
        dc->dml.ip.bug_forcing_LC_req_same_size_fixed =
                dc->dcn_ip->bug_forcing_luma_and_chroma_request_to_same_size_fixed == dcn_bw_yes;
        dc->dml.ip.dcfclk_cstate_latency = dc->dcn_ip->dcfclk_cstate_latency;
-       kernel_fpu_end();
+       DC_FP_END();
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
index cfc6991..1e8b79b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c
@@ -1,5 +1,6 @@
 /*
 * Copyright 2016 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -3211,7 +3212,7 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
 
 void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb)
 {
-       kernel_fpu_begin();
+       DC_FP_START();
        if ((int)(bb->sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns
                        && dc->bb_overrides.sr_exit_time_ns) {
                bb->sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;
@@ -3235,7 +3236,7 @@ void dcn20_patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st
                bb->dram_clock_change_latency_us =
                                dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;
        }
-       kernel_fpu_end();
+       DC_FP_END();
 }
 
 static struct _vcs_dpi_soc_bounding_box_st *get_asic_rev_soc_bb(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
index c865b95..1282727 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
@@ -1,5 +1,6 @@
 /*
 * Copyright 2018 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -993,7 +994,8 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
 {
        int i;
 
-       kernel_fpu_begin();
+       DC_FP_START();
+
        if (dc->bb_overrides.sr_exit_time_ns) {
                for (i = 0; i < WM_SET_COUNT; i++) {
                          dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us =
@@ -1019,7 +1021,7 @@ static void patch_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
                }
        }
 
-       kernel_fpu_end();
+       DC_FP_END();
 }
 
 void dcn21_calculate_wm(

diff --git a/drivers/gpu/drm/amd/display/dc/os_types.h b/drivers/gpu/drm/amd/display/dc/os_types.h
index 13b9a9b..ffb4438 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/os_types.h
+++ b/drivers/gpu/drm/amd/display/dc/os_types.h
@@ -1,5 +1,6 @@
 /*
  * Copyright 2012-16 Advanced Micro Devices, Inc.
+ * Copyright 2019 Raptor Engineering, LLC
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -51,6 +52,8 @@
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
 #include <asm/fpu/api.h>
+#define DC_FP_START() kernel_fpu_begin()
+#define DC_FP_END() kernel_fpu_end()
 #endif
 
 /*