intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder =
intel_get_crtc_new_encoder(state, crtc_state);
- int ret;
if (DISPLAY_VER(dev_priv) < 11 &&
intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
return 0;
- ret = intel_reserve_shared_dplls(state, crtc, encoder);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "failed to find PLL for pipe %c\n",
- pipe_name(crtc->pipe));
- return ret;
- }
-
- return 0;
+ return intel_reserve_shared_dplls(state, crtc, encoder);
}
static int dg2_crtc_compute_clock(struct intel_atomic_state *state,
if (!crtc_state->clock_set &&
!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
ilk_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
- int ret;
/* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
if (!crtc_state->has_pch_encoder)
return 0;
- ret = intel_reserve_shared_dplls(state, crtc, NULL);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "failed to find PLL for pipe %c\n",
- pipe_name(crtc->pipe));
- return ret;
- }
-
- return 0;
+ return intel_reserve_shared_dplls(state, crtc, NULL);
}
void vlv_compute_dpll(struct intel_crtc_state *crtc_state)
static int chv_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = &intel_limits_chv;
if (!crtc_state->clock_set &&
!chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
chv_compute_dpll(crtc_state);
static int vlv_crtc_compute_clock(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
const struct intel_limit *limit = &intel_limits_vlv;
if (!crtc_state->clock_set &&
!vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
refclk, NULL, &crtc_state->dpll)) {
- drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n");
return -EINVAL;
}
if (!crtc_state->clock_set &&
!g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
if (!crtc_state->clock_set &&
!pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
if (!crtc_state->clock_set &&
!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
i9xx_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
if (!crtc_state->clock_set &&
!i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock,
- refclk, NULL, &crtc_state->dpll)) {
- drm_err(&dev_priv->drm,
- "Couldn't find PLL settings for mode!\n");
+ refclk, NULL, &crtc_state->dpll))
return -EINVAL;
- }
i8xx_compute_dpll(crtc_state, &crtc_state->dpll,
&crtc_state->dpll);
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ int ret;
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
if (!crtc_state->hw.enable)
return 0;
- return i915->dpll_funcs->crtc_compute_clock(state, crtc);
+ ret = i915->dpll_funcs->crtc_compute_clock(state, crtc);
+ if (ret) {
+ drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n",
+ crtc->base.base.id, crtc->base.name);
+ return ret;
+ }
+
+ return 0;
}
int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state,
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
+ int ret;
drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state));
if (!i915->dpll_funcs->crtc_get_shared_dpll)
return 0;
- return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+ ret = i915->dpll_funcs->crtc_get_shared_dpll(state, crtc);
+ if (ret) {
+ drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n",
+ crtc->base.base.id, crtc->base.name);
+ return ret;
+ }
+
+ return 0;
}
void
break;
}
- if (!ctx.p) {
- DRM_DEBUG_DRIVER("No valid divider found for %dHz\n", clock);
+ if (!ctx.p)
return -EINVAL;
- }
/*
* gcc incorrectly analyses that these can be used without being
struct dpll *clk_div)
{
struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
/* Calculate HDMI div */
/*
* FIXME: tie the following calculation into
* i9xx_crtc_compute_clock
*/
- if (!bxt_find_best_dpll(crtc_state, clk_div)) {
- drm_dbg(&i915->drm, "no PLL dividers found for clock %d pipe %c\n",
- crtc_state->port_clock,
- pipe_name(crtc->pipe));
+ if (!bxt_find_best_dpll(crtc_state, clk_div))
return -EINVAL;
- }
drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
pll_state, is_dkl);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to find divisors for clock %d\n", clock);
+ if (ret)
return ret;
- }
m1div = 2;
m2div_int = dco_khz / (refclk_khz * m1div);
m2div_int = dco_khz / (refclk_khz * m1div);
}
- if (m2div_int > 255) {
- drm_dbg_kms(&dev_priv->drm,
- "Failed to find mdiv for clock %d\n",
- clock);
+ if (m2div_int > 255)
return -EINVAL;
- }
}
m2div_rem = dco_khz % (refclk_khz * m1div);
else
ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Could not calculate combo PHY PLL state.\n");
+ if (ret)
return ret;
- }
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,
dpll_mask);
- if (!port_dpll->pll) {
- drm_dbg_kms(&dev_priv->drm,
- "No combo PHY PLL found for [ENCODER:%d:%s]\n",
- encoder->base.base.id, encoder->base.name);
+ if (!port_dpll->pll)
return -EINVAL;
- }
intel_reference_shared_dpll(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
ret = icl_calc_tbt_pll(crtc_state, &pll_params);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Could not calculate TBT PLL state.\n");
+ if (ret)
return ret;
- }
icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
- if (ret) {
- drm_dbg_kms(&dev_priv->drm,
- "Could not calculate MG PHY PLL state.\n");
+ if (ret)
return ret;
- }
return 0;
}
port_dpll->pll = intel_find_shared_dpll(state, crtc,
&port_dpll->hw_state,
BIT(DPLL_ID_ICL_TBTPLL));
- if (!port_dpll->pll) {
- drm_dbg_kms(&dev_priv->drm, "No TBT-ALT PLL found\n");
+ if (!port_dpll->pll)
return -EINVAL;
- }
intel_reference_shared_dpll(state, crtc,
port_dpll->pll, &port_dpll->hw_state);
BIT(dpll_id));
if (!port_dpll->pll) {
ret = -EINVAL;
- drm_dbg_kms(&dev_priv->drm, "No MG PHY PLL found\n");
goto err_unreference_tbt_pll;
}
intel_reference_shared_dpll(state, crtc,