intel/eu/gen12: Add Gen12 opcode descriptions to the table.

Quite a lot of churn because the encoding of most hardware opcodes has
changed unfortunately.

v2: Split dot-product description fixes to separate patch (Caio).

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

diff --git a/src/intel/compiler/brw_eu.cpp b/src/intel/compiler/brw_eu.cpp
index 11bdddc..a8c3e55 100644 (file)
--- a/src/intel/compiler/brw_eu.cpp
+++ b/src/intel/compiler/brw_eu.cpp
@@ -456,6 +456,7 @@ enum gen {
    GEN9  = (1 << 7),
    GEN10 = (1 << 8),
    GEN11 = (1 << 9),
+   GEN12 = (1 << 10),
    GEN_ALL = ~0
 };
 
@@ -466,29 +467,49 @@ enum gen {
 static const struct opcode_desc opcode_descs[] = {
    /* IR,                 HW,  name,      nsrc, ndst, gens */
    { BRW_OPCODE_ILLEGAL,  0,   "illegal", 0,    0,    GEN_ALL },
-   { BRW_OPCODE_MOV,      1,   "mov",     1,    1,    GEN_ALL },
-   { BRW_OPCODE_SEL,      2,   "sel",     2,    1,    GEN_ALL },
-   { BRW_OPCODE_MOVI,     3,   "movi",    2,    1,    GEN_GE(GEN45) },
-   { BRW_OPCODE_NOT,      4,   "not",     1,    1,    GEN_ALL },
-   { BRW_OPCODE_AND,      5,   "and",     2,    1,    GEN_ALL },
-   { BRW_OPCODE_OR,       6,   "or",      2,    1,    GEN_ALL },
-   { BRW_OPCODE_XOR,      7,   "xor",     2,    1,    GEN_ALL },
-   { BRW_OPCODE_SHR,      8,   "shr",     2,    1,    GEN_ALL },
-   { BRW_OPCODE_SHL,      9,   "shl",     2,    1,    GEN_ALL },
+   { BRW_OPCODE_MOV,      1,   "mov",     1,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_MOV,      97,  "mov",     1,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_SEL,      2,   "sel",     2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_SEL,      98,  "sel",     2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_MOVI,     3,   "movi",    2,    1,    GEN_GE(GEN45) & GEN_LT(GEN12) },
+   { BRW_OPCODE_MOVI,     99,  "movi",    2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_NOT,      4,   "not",     1,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_NOT,      100, "not",     1,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_AND,      5,   "and",     2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_AND,      101, "and",     2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_OR,       6,   "or",      2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_OR,       102, "or",      2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_XOR,      7,   "xor",     2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_XOR,      103, "xor",     2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_SHR,      8,   "shr",     2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_SHR,      104, "shr",     2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_SHL,      9,   "shl",     2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_SHL,      105, "shl",     2,    1,    GEN_GE(GEN12) },
    { BRW_OPCODE_DIM,      10,  "dim",     1,    1,    GEN75 },
-   { BRW_OPCODE_SMOV,     10,  "smov",    0,    0,    GEN_GE(GEN8) },
-   { BRW_OPCODE_ASR,      12,  "asr",     2,    1,    GEN_ALL },
-   { BRW_OPCODE_ROR,      14,  "ror",     2,    1,    GEN_GE(GEN11) },
-   { BRW_OPCODE_ROL,      15,  "rol",     2,    1,    GEN_GE(GEN11) },
-   { BRW_OPCODE_CMP,      16,  "cmp",     2,    1,    GEN_ALL },
-   { BRW_OPCODE_CMPN,     17,  "cmpn",    2,    1,    GEN_ALL },
-   { BRW_OPCODE_CSEL,     18,  "csel",    3,    1,    GEN_GE(GEN8) },
+   { BRW_OPCODE_SMOV,     10,  "smov",    0,    0,    GEN_GE(GEN8) & GEN_LT(GEN12) },
+   { BRW_OPCODE_SMOV,     106, "smov",    0,    0,    GEN_GE(GEN12) },
+   { BRW_OPCODE_ASR,      12,  "asr",     2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_ASR,      108, "asr",     2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_ROR,      14,  "ror",     2,    1,    GEN11 },
+   { BRW_OPCODE_ROR,      110, "ror",     2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_ROL,      15,  "rol",     2,    1,    GEN11 },
+   { BRW_OPCODE_ROL,      111, "rol",     2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_CMP,      16,  "cmp",     2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_CMP,      112, "cmp",     2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_CMPN,     17,  "cmpn",    2,    1,    GEN_LT(GEN12) },
+   { BRW_OPCODE_CMPN,     113, "cmpn",    2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_CSEL,     18,  "csel",    3,    1,    GEN_GE(GEN8) & GEN_LT(GEN12) },
+   { BRW_OPCODE_CSEL,     114, "csel",    3,    1,    GEN_GE(GEN12) },
    { BRW_OPCODE_F32TO16,  19,  "f32to16", 1,    1,    GEN7 | GEN75 },
    { BRW_OPCODE_F16TO32,  20,  "f16to32", 1,    1,    GEN7 | GEN75 },
-   { BRW_OPCODE_BFREV,    23,  "bfrev",   1,    1,    GEN_GE(GEN7) },
-   { BRW_OPCODE_BFE,      24,  "bfe",     3,    1,    GEN_GE(GEN7) },
-   { BRW_OPCODE_BFI1,     25,  "bfi1",    2,    1,    GEN_GE(GEN7) },
-   { BRW_OPCODE_BFI2,     26,  "bfi2",    3,    1,    GEN_GE(GEN7) },
+   { BRW_OPCODE_BFREV,    23,  "bfrev",   1,    1,    GEN_GE(GEN7) & GEN_LT(GEN12) },
+   { BRW_OPCODE_BFREV,    119, "bfrev",   1,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_BFE,      24,  "bfe",     3,    1,    GEN_GE(GEN7) & GEN_LT(GEN12) },
+   { BRW_OPCODE_BFE,      120, "bfe",     3,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_BFI1,     25,  "bfi1",    2,    1,    GEN_GE(GEN7) & GEN_LT(GEN12) },
+   { BRW_OPCODE_BFI1,     121, "bfi1",    2,    1,    GEN_GE(GEN12) },
+   { BRW_OPCODE_BFI2,     26,  "bfi2",    3,    1,    GEN_GE(GEN7) & GEN_LT(GEN12) },
+   { BRW_OPCODE_BFI2,     122, "bfi2",    3,    1,    GEN_GE(GEN12) },
    { BRW_OPCODE_JMPI,     32,  "jmpi",    0,    0,    GEN_ALL },
    { BRW_OPCODE_BRD,      33,  "brd",     0,    0,    GEN_GE(GEN7) },
    { BRW_OPCODE_IF,       34,  "if",      0,    0,    GEN_ALL },
@@ -511,11 +532,11 @@ static const struct opcode_desc opcode_descs[] = {
    { BRW_OPCODE_FORK,     46,  "fork",    0,    0,    GEN6 },
    { BRW_OPCODE_GOTO,     46,  "goto",    0,    0,    GEN_GE(GEN8) },
    { BRW_OPCODE_POP,      47,  "pop",     2,    0,    GEN_LE(GEN5) },
-   { BRW_OPCODE_WAIT,     48,  "wait",    1,    0,    GEN_ALL },
+   { BRW_OPCODE_WAIT,     48,  "wait",    1,    0,    GEN_LT(GEN12) },
    { BRW_OPCODE_SEND,     49,  "send",    1,    1,    GEN_ALL },
    { BRW_OPCODE_SENDC,    50,  "sendc",   1,    1,    GEN_ALL },
-   { BRW_OPCODE_SENDS,    51,  "sends",   2,    1,    GEN_GE(GEN9) },
-   { BRW_OPCODE_SENDSC,   52,  "sendsc",  2,    1,    GEN_GE(GEN9) },
+   { BRW_OPCODE_SENDS,    51,  "sends",   2,    1,    GEN_GE(GEN9) & GEN_LT(GEN12) },
+   { BRW_OPCODE_SENDSC,   52,  "sendsc",  2,    1,    GEN_GE(GEN9) & GEN_LT(GEN12) },
    { BRW_OPCODE_MATH,     56,  "math",    2,    1,    GEN_GE(GEN6) },
    { BRW_OPCODE_ADD,      64,  "add",     2,    1,    GEN_ALL },
    { BRW_OPCODE_MUL,      65,  "mul",     2,    1,    GEN_ALL },
@@ -545,7 +566,8 @@ static const struct opcode_desc opcode_descs[] = {
    { BRW_OPCODE_LRP,      92,  "lrp",     3,    1,    GEN_GE(GEN6) & GEN_LE(GEN10) },
    { BRW_OPCODE_MADM,     93,  "madm",    3,    1,    GEN_GE(GEN8) },
    { BRW_OPCODE_NENOP,    125, "nenop",   0,    0,    GEN45 },
-   { BRW_OPCODE_NOP,      126, "nop",     0,    0,    GEN_ALL },
+   { BRW_OPCODE_NOP,      126, "nop",     0,    0,    GEN_LT(GEN12) },
+   { BRW_OPCODE_NOP,      96,  "nop",     0,    0,    GEN_GE(GEN12) }
 };
 
 static enum gen
@@ -560,6 +582,7 @@ gen_from_devinfo(const struct gen_device_info *devinfo)
    case 9: return GEN9;
    case 10: return GEN10;
    case 11: return GEN11;
+   case 12: return GEN12;
    default:
       unreachable("not reached");
    }