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target/riscv: fix a typo with interrupt names
authorEmmanuel Blot <emmanuel.blot@sifive.com>
Wed, 21 Apr 2021 13:32:36 +0000 (15:32 +0200)
committerAlistair Francis <alistair.francis@wdc.com>
Tue, 11 May 2021 10:02:07 +0000 (20:02 +1000)
Interrupt names have been swapped in 205377f8 and do not follow
IRQ_*_EXT definition order.

Signed-off-by: Emmanuel Blot <emmanuel.blot@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210421133236.11323-1-emmanuel.blot@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c

index 4bf6a00..04ac03f 100644 (file)
@@ -88,8 +88,8 @@ const char * const riscv_intr_names[] = {
     "vs_timer",
     "m_timer",
     "u_external",
+    "s_external",
     "vs_external",
-    "h_external",
     "m_external",
     "reserved",
     "reserved",