}
pci = PCI_HOST_BRIDGE(dev);
+ pci->bypass_iommu = vms->default_bus_bypass_iommu;
vms->bus = pci->bus;
if (vms->bus) {
for (i = 0; i < nb_nics; i++) {
}
}
+static bool virt_get_default_bus_bypass_iommu(Object *obj, Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ return vms->default_bus_bypass_iommu;
+}
+
+static void virt_set_default_bus_bypass_iommu(Object *obj, bool value,
+ Error **errp)
+{
+ VirtMachineState *vms = VIRT_MACHINE(obj);
+
+ vms->default_bus_bypass_iommu = value;
+}
+
static CpuInstanceProperties
virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index)
{
"Set the IOMMU type. "
"Valid values are none and smmuv3");
+ object_class_property_add_bool(oc, "default_bus_bypass_iommu",
+ virt_get_default_bus_bypass_iommu,
+ virt_set_default_bus_bypass_iommu);
+ object_class_property_set_description(oc, "default_bus_bypass_iommu",
+ "Set on/off to enable/disable "
+ "bypass_iommu for default root bus");
+
object_class_property_add_bool(oc, "ras", virt_get_ras,
virt_set_ras);
object_class_property_set_description(oc, "ras",
/* Default disallows iommu instantiation */
vms->iommu = VIRT_IOMMU_NONE;
+ /* The default root bus is attached to iommu by default */
+ vms->default_bus_bypass_iommu = false;
+
/* Default disallows RAS instantiation */
vms->ras = false;