reset vector ok

diff --git a/de1_nes/cpu/alu.vhd b/de1_nes/cpu/alu.vhd
index 1360bca..3543536 100644 (file)
--- a/de1_nes/cpu/alu.vhd
+++ b/de1_nes/cpu/alu.vhd
@@ -302,7 +302,6 @@ end  procedure;
         --get next address.
         inc_addr(bal);
         abl <= addr_out;
-
         ea_carry <= addr_c;
 
     elsif (indir_x_n = '0') then
@@ -413,8 +412,12 @@ end  procedure;
         ea_carry <= '0';
         addr_back_l <= (others => 'Z');
         addr_back_h <= (others => 'Z');
-        abl <= "11111100";
         abh <= "11111111";
+        if (addr_cycle = ADDR_Z) then
+            abl <= "11111100";
+        else
+            abl <= "11111101";
+        end if;
 
     elsif (n_vec_oe_n = '0') then
         ea_carry <= '0';

diff --git a/de1_nes/cpu/decoder.vhd b/de1_nes/cpu/decoder.vhd
index 6f9d2c1..1e05b89 100644 (file)
--- a/de1_nes/cpu/decoder.vhd
+++ b/de1_nes/cpu/decoder.vhd
@@ -2877,7 +2877,7 @@ end  procedure;
                 r_nw <= '1';
                 dbuf_int_oe_n <= '0';
                 front_we(pch_cmd, '0');
-                indir_n <= '0';
+                addr_cycle <= ADDR_T2;
 
                 if wk_exec_cycle = N6 then
                     nmi_handled_n <= '0';

diff --git a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
index 3b2ec69..20ae0b0 100644 (file)
--- a/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
+++ b/de1_nes/simulation/modelsim/de1_nes_run_msim_rtl_vhdl.do
@@ -58,6 +58,9 @@ add wave -label sp -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/sp/q
 add wave -label x -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/x/q\r
 add wave -label y -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/y/q\r
 \r
+add wave -label pcl -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pcl_inst/q\r
+add wave -label pch -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/pch_inst/q\r
+\r
 \r
 ##add wave -radix hex sim:/testbench_motones_sim/sim_board/cpu_inst/status_reg\r
 \r