add support for branch on ordered/unordered.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24067 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index d078bdc..3d9cd8d 100644 (file)
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -489,6 +489,15 @@ static unsigned getBCCForSetCC(ISD::CondCode CC) {
   case ISD::SETGT:  return PPC::BGT;
   case ISD::SETUGE:
   case ISD::SETGE:  return PPC::BGE;
+    
+  case ISD::SETO:   return PPC::BUN;
+  case ISD::SETUO:  return PPC::BNU;
+  case ISD::SETOEQ:
+  case ISD::SETOGT:
+  case ISD::SETOGE:
+  case ISD::SETOLT:
+  case ISD::SETOLE:
+  case ISD::SETONE: assert(0 && "Unknown condition!"); abort();
   }
   return 0;
 }
@@ -509,6 +518,14 @@ static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool& Inv) {
   case ISD::SETLE:  Inv = true;   return 1;
   case ISD::SETEQ:  Inv = false;  return 2;
   case ISD::SETNE:  Inv = true;   return 2;
+  case ISD::SETO:   Inv = true;   return 3;
+  case ISD::SETUO:  Inv = false;  return 3;
+  case ISD::SETOEQ:
+  case ISD::SETOGT:
+  case ISD::SETOGE:
+  case ISD::SETOLT:
+  case ISD::SETOLE:
+  case ISD::SETONE: assert(0 && "Unknown condition!"); abort();
   }
   return 0;
 }

diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index e858440..73362a9 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -204,6 +204,10 @@ let isBranch = 1, isTerminator = 1 in {
                   "bgt $crS, $block", BrB>;
   def BNE : BForm<16, 0, 0, 4,  2, (ops CRRC:$crS, target:$block),
                   "bne $crS, $block", BrB>;
+  def BUN : BForm<16, 0, 0, 12, 3, (ops CRRC:$crS, target:$block),
+                  "bun $crS, $block", BrB>;
+  def BNU : BForm<16, 0, 0, 4,  3, (ops CRRC:$crS, target:$block),
+                  "bnu $crS, $block", BrB>;
 }
 
 let isCall = 1,