if (Subtarget->isThumb()) {
if (Val <= 255) return 1; // MOV
if (Subtarget->hasV6T2Ops() && Val <= 0xffff) return 1; // MOVW
+ if (Val <= 511) return 2; // MOV + ADDi8
if (~Val <= 255) return 2; // MOV + MVN
if (ARM_AM::isThumbImmShiftedVal(Val)) return 2; // MOV + LSL
} else {
return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
}]>;
+def imm256_511 : ImmLeaf<i32, [{
+ return Imm >= 256 && Imm < 512;
+}]>;
+
+def thumb_imm256_511_addend : SDNodeXForm<imm, [{
+ return CurDAG->getTargetConstant(N->getZExtValue() - 255, SDLoc(N), MVT::i32);
+}]>;
+
// Scaled 4 immediate.
def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
def t_imm0_1020s4 : Operand<i32> {
def : T1Pat<(i32 imm0_255_comp:$src),
(tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
+def : T1Pat<(i32 imm256_511:$src),
+ (tADDi8 (tMOVi8 255),
+ (thumb_imm256_511_addend imm:$src))>;
+
// Pseudo instruction that combines ldr from constpool and add pc. This should
// be expanded into two instructions late to allow if-conversion and
// scheduling.
--- /dev/null
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m0 -verify-machineinstrs | FileCheck --check-prefix CHECK-T1 %s
+; RUN: llc < %s -mtriple=thumbv7-linux-gnueabi -mcpu=cortex-m3 -verify-machineinstrs | FileCheck --check-prefix CHECK-T2 %s
+
+; CHECK-T1-LABEL: @mov_and_add
+; CHECK-T2-LABEL: @mov_and_add
+; CHECK-T1: movs r0, #255
+; CHECK-T1: adds r0, #12
+; CHECK-T2: movw r0, #267
+define i32 @mov_and_add() {
+ ret i32 267
+}