vga_top修正バージョン

チェック柄出力確認。
アドレスのずれが発生して画面がスライドするので、
アドレス計算の部分を修正。
未検証

Change-Id: If4d80dba6efc7b212d05f5d9fa4f482ee91b6b34

diff --git a/VGADisplay/src/push_sw.nsl b/VGADisplay/src/push_sw.nsl
new file mode 100644 (file)
index 0000000..2277089
--- /dev/null
+++ b/VGADisplay/src/push_sw.nsl
@@ -0,0 +1,46 @@
+/**\r
+*      Push switch module\r
+*      Module name "push_sw"\r
+*      @author         Yujiro Kaneko\r
+*      @version        0.1\r
+*/\r
+\r
+#define CNT_1ms 19'd500000             // Count value for 1m sec at 50MHz\r
+//#define CNT_1ms 26'd50               // Count value for test\r
+\r
+#define TRUE   1'd1\r
+#define FALSE  1'd0\r
+\r
+declare push_sw {\r
+       input    i_sw ;                         // Button signal input terminal\r
+       func_out fo_sw_enb ;            // Button enable signal\r
+}\r
+module push_sw {\r
+       reg r_cnt[19]     = 19'd0 ;     // Button enable count\r
+       reg r_rise_flag   = FALSE ;     // Button signal rising flag\r
+       reg r_sw_hld      = 0 ;         //\r
+       reg r_finish_flag = FALSE ;     // "fo_btn_enb" transfer flag\r
+\r
+       r_sw_hld := i_sw ;\r
+\r
+       if( i_sw & ~r_sw_hld ) {\r
+               r_rise_flag := TRUE ;\r
+       } else if( ~i_sw ) {\r
+               r_rise_flag := FALSE ;\r
+               r_finish_flag := FALSE ;\r
+       }\r
+       \r
+       if( r_rise_flag == TRUE ){\r
+               any {\r
+                       ( r_cnt == CNT_1ms ) & ( r_finish_flag == FALSE ) : {\r
+                               r_finish_flag := TRUE ;\r
+                               fo_sw_enb() ;\r
+                       }\r
+                       else : {\r
+                               r_cnt++ ;\r
+                       }\r
+               }\r
+       } else {\r
+               r_cnt := 26'd0 ;\r
+       }\r
+}
\ No newline at end of file

diff --git a/VGADisplay/src/vga_gen.nsl b/VGADisplay/src/vga_gen.nsl
index 8d4970c..1d099c4 100644 (file)
--- a/VGADisplay/src/vga_gen.nsl
+++ b/VGADisplay/src/vga_gen.nsl
@@ -114,7 +114,7 @@ module vga_gen {
                
                
                // HACTMAX640 VACTMAX480 \83J\83\89\81[\95`\89æ\83G\83\8a\83A
-               if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) ) {
+               if( ( r_hcnt < H_ACT_MAX ) && ( r_vcnt < V_ACT_MAX ) && r_vsync ) {
 
                        // \83f\81[\83^\83o\83b\83t\83@\89^\97p\83J\83E\83\93\83^\81i\83e\83X\83g\97p\81j
                        if( r_init_flg ) {
@@ -175,6 +175,14 @@ module vga_gen {
                                        r_hsync := 1 ;
                                }
                        }
+
+                       // FIFO\93Ç\82Ý\8fo\82µ\92l\83o\83b\83t\83@\83\8a\83\93\83O
+                       if( fs_fifo_ack ) {
+                               any {
+                                       ~r_reg_cnt      : r_data2 := w_rddata ;
+                                       r_reg_cnt       : r_data1 := w_rddata ;
+                               }
+                       }
                }
 
                any {
@@ -182,7 +190,8 @@ module vga_gen {
                        r_vcnt == V_FRONTP_MAX  : r_vsync := 0 ;
                        r_vcnt == V_SYNC_MAX    : r_vsync := 1 ;
                }
-       }
+
+       }       // public end ;
        
        // VGA Gen initialize command
        func fs_initialize seq {

diff --git a/VGADisplay/src/vga_ram.v b/VGADisplay/src/vga_ram.v
index ea2bf3a..70bef6e 100644 (file)
--- a/VGADisplay/src/vga_ram.v
+++ b/VGADisplay/src/vga_ram.v
@@ -23,10 +23,10 @@ module vga_ram (
        (* remstyle = "no_rw_check" *) reg [7:0] mem1[511:0] ;
 
        assign o_rddata = mem1[r_rdadrs] ;
-       assign o_rdack = (r_rdadrs_buff != r_rdadrs[9]) ;
+       assign o_rdack = (r_rdadrs_buff != r_rdadrs[8]) ;
        
        always @( posedge i_clk50 ) begin
-               r_rdadrs_buff <= r_rdadrs[9] ;
+               r_rdadrs_buff <= r_rdadrs[8] ;
        end
        
        // memory read command
@@ -35,7 +35,8 @@ module vga_ram (
                        r_rdadrs <= 0 ;
                end
                else if( i_re ) begin
-                       r_rdadrs <= r_rdadrs + 9'd1 ;
+                       if(r_rdadrs < 480)      r_rdadrs <= r_rdadrs + 9'd1 ;
+                       else                            r_rdadrs <= 9'd0 ;
                end
        end
 
@@ -46,7 +47,9 @@ module vga_ram (
                end
                else if( i_we ) begin
                        mem1[r_wradrs] <= i_wrdata ;
-                       r_wradrs <= r_wradrs + 9'd1 ;
+
+                       if(r_wradrs < 480)      r_wradrs <= r_wradrs + 9'd1 ;
+                       else                            r_wradrs <= 9'd0 ;
                end
        end
 endmodule
\ No newline at end of file

diff --git a/VGADisplay/src/vga_top.nsl b/VGADisplay/src/vga_top.nsl
index 6291e3f..cd212fd 100644 (file)
--- a/VGADisplay/src/vga_top.nsl
+++ b/VGADisplay/src/vga_top.nsl
@@ -111,18 +111,18 @@ module vga_top {
                trigger := { trigger[1:0], 0b1 } ;\r
                if(trigger == 3'b011) fs_init() ;\r
 \r
-/*\r
-               if(~r_reset) {\r
-                       any {\r
-                               r_hld_vram_start & ~u_VGA.o_vcnt[0] : { //FIFO1\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
-                                       if(u_VGA.o_vcnt < 10'd480) fs_fifo2_charge() ;\r
-                               }\r
-                               ~r_hld_vram_start & u_VGA.o_vcnt[0] : { //FIFO2\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
-                                       if(u_VGA.o_vcnt < 10'd480) fs_fifo1_charge() ;\r
-                               }\r
-                       }\r
-               }\r
-*/\r
+\r
+//             if(~r_reset) {\r
+//                     any {\r
+//                             r_hld_vram_start & ~u_VGA.o_vcnt[0] : { //FIFO1\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
+//                                     if(u_VGA.o_vcnt < 10'd480) fs_fifo2_charge() ;\r
+//                             }\r
+//                             ~r_hld_vram_start & u_VGA.o_vcnt[0] : { //FIFO2\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
+//                                     if(u_VGA.o_vcnt < 10'd480) fs_fifo1_charge() ;\r
+//                             }\r
+//                     }\r
+//             }\r
+\r
 \r
                any {\r
                        r_sec_cnt == CNT1S : {\r
@@ -192,9 +192,13 @@ module vga_top {
                r_fifo_rst := 0 ;\r
                ;;;\r
 \r
-               for(r_init_cnt:=0; r_init_cnt<512; r_init_cnt++ ) {\r
-                       u_VGA.fi_fifo_write(r_init_cnt[7:0]) ;\r
-                       u_VGA.fi_fifo_write(r_init_cnt[7:0]) ;\r
+               for(r_init_cnt:=0; r_init_cnt<120; r_init_cnt++ ) {\r
+                       u_VGA.fi_fifo_write(8'hFF) ;\r
+                       u_VGA.fi_fifo_write(8'h00) ;\r
+               }\r
+               for(r_init_cnt:=0; r_init_cnt<120; r_init_cnt++ ) {\r
+                       u_VGA.fi_fifo_write(8'h00) ;\r
+                       u_VGA.fi_fifo_write(8'hFF) ;\r
                }               \r
 \r
                r_reset := 0 ;          \r