val = env->fsr;
break;
case GDB_BTR:
- val = env->sregs[SR_BTR];
+ val = env->btr;
break;
case GDB_PVR0 ... GDB_PVR11:
/* PVR12 is intentionally skipped */
env->fsr = tmp;
break;
case GDB_BTR:
- env->sregs[SR_BTR] = tmp;
+ env->btr = tmp;
break;
case GDB_PVR0 ... GDB_PVR11:
/* PVR12 is intentionally skipped */
/* Exception breaks branch + dslot sequence? */
if (env->iflags & D_FLAG) {
env->esr |= 1 << 12 ;
- env->sregs[SR_BTR] = env->btarget;
+ env->btr = env->btarget;
}
/* Disable the MMU. */
if (env->iflags & D_FLAG) {
D(qemu_log("D_FLAG set at exception bimm=%d\n", env->bimm));
env->esr |= 1 << 12 ;
- env->sregs[SR_BTR] = env->btarget;
+ env->btr = env->btarget;
/* Reexecute the branch. */
env->regs[17] -= 4;
"rbtr=%" PRIx64 "\n",
env->msr, env->esr, env->ear,
env->debug, env->imm, env->iflags, env->fsr,
- env->sregs[SR_BTR]);
+ env->btr);
qemu_fprintf(f, "btaken=%d btarget=%" PRIx64 " mode=%s(saved=%s) "
"eip=%d ie=%d\n",
env->btaken, env->btarget,
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, esr), "resr");
cpu_SR[SR_FSR] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
+ cpu_SR[SR_BTR] =
+ tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr");
- for (i = SR_FSR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
+ for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);