adc test added.

diff --git a/simulation/cpu/alu/alu.vhd b/simulation/cpu/alu/alu.vhd
index 5eb96ed..bf092c5 100644 (file)
--- a/simulation/cpu/alu/alu.vhd
+++ b/simulation/cpu/alu/alu.vhd
@@ -26,7 +26,7 @@ architecture rtl of alu is
 begin
     adc_port : adc port map (a, b, adc_o, cin, adc_cout, adc_n, adc_v, adc_z);
 
-    p : process (adc_o)
+    p : process (a, b, m, cin, adc_o)
     begin
     case m(7 downto 5) is
         when "011" =>

diff --git a/simulation/cpu/alu/testbench_alu.vhd b/simulation/cpu/alu/testbench_alu.vhd
index 4158de9..84ee253 100644 (file)
--- a/simulation/cpu/alu/testbench_alu.vhd
+++ b/simulation/cpu/alu/testbench_alu.vhd
@@ -60,6 +60,30 @@ begin
         ccin <= '0';
         wait for interval;
 
+        write(out_line, string'("adc test 4"));
+        writeline(output, out_line);
+        aa <= conv_std_logic_vector(10#40#, 8);
+        bb <= conv_std_logic_vector(10#120#, 8);
+        mm <= "01111111";
+        ccin <= '0';
+        wait for interval;
+
+        write(out_line, string'("adc test 5"));
+        writeline(output, out_line);
+        aa <= conv_std_logic_vector(10#40#, 8);
+        bb <= conv_std_logic_vector(10#51#, 8);
+        mm <= "01111111";
+        ccin <= '0';
+        wait for interval;
+
+        write(out_line, string'("adc test 6"));
+        writeline(output, out_line);
+        aa <= x"f5";
+        bb <= x"14";
+        mm <= "01111111";
+        ccin <= '0';
+        wait for interval;
+
         write(out_line, string'("test done"));
         writeline(output, out_line);
         wait;