void DispatchStage::notifyInstructionDispatched(const InstRef &IR,
ArrayRef<unsigned> UsedRegs) {
- LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: " << IR << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Instruction Dispatched: #" << IR << '\n');
notifyEvent<HWInstructionEvent>(HWInstructionDispatchedEvent(IR, UsedRegs));
}
collectWrites(DependentWrites, RS.getRegisterID());
RS.setDependentWrites(DependentWrites.size());
- LLVM_DEBUG(dbgs() << "Found " << DependentWrites.size()
- << " dependent writes\n");
// We know that this read depends on all the writes in DependentWrites.
// For each write, check if we have ReadAdvance information, and use it
// to figure out in how many cycles this read becomes available.
if (!HWS.issueImmediately(IR))
return true;
- LLVM_DEBUG(dbgs() << "[SCHEDULER] Instruction " << IR
+ LLVM_DEBUG(dbgs() << "[SCHEDULER] Instruction #" << IR
<< " issued immediately\n");
// Issue IR. The resources for this issuance will be placed in 'Used.'
void ExecuteStage::notifyInstructionExecuted(const InstRef &IR) {
HWS.onInstructionExecuted(IR);
- LLVM_DEBUG(dbgs() << "[E] Instruction Executed: " << IR << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Instruction Executed: #" << IR << '\n');
notifyEvent<HWInstructionEvent>(
HWInstructionEvent(HWInstructionEvent::Executed, IR));
RCU.onInstructionExecuted(IR.getInstruction()->getRCUTokenID());
}
void ExecuteStage::notifyInstructionReady(const InstRef &IR) {
- LLVM_DEBUG(dbgs() << "[E] Instruction Ready: " << IR << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Instruction Ready: #" << IR << '\n');
notifyEvent<HWInstructionEvent>(
HWInstructionEvent(HWInstructionEvent::Ready, IR));
}
void ExecuteStage::notifyInstructionIssued(
const InstRef &IR, ArrayRef<std::pair<ResourceRef, double>> Used) {
LLVM_DEBUG({
- dbgs() << "[E] Instruction Issued: " << IR << '\n';
+ dbgs() << "[E] Instruction Issued: #" << IR << '\n';
for (const std::pair<ResourceRef, unsigned> &Resource : Used) {
dbgs() << "[E] Resource Used: [" << Resource.first.first << '.'
- << Resource.first.second << "]\n";
- dbgs() << " cycles: " << Resource.second << '\n';
+ << Resource.first.second << "], ";
+ dbgs() << "cycles: " << Resource.second << '\n';
}
});
notifyEvent<HWInstructionEvent>(HWInstructionIssuedEvent(IR, Used));
}
Write.IsOptionalDef = false;
LLVM_DEBUG({
- dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", Latency=" << Write.Latency
+ dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
+ << ", Latency=" << Write.Latency
<< ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
});
CurrentDef++;
Write.IsOptionalDef = false;
assert(Write.RegisterID != 0 && "Expected a valid phys register!");
- LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Write.OpIndex << ", PhysReg="
- << Write.RegisterID << ", Latency=" << Write.Latency
- << ", WriteResourceID=" << Write.SClassOrWriteResourceID
- << '\n');
+ LLVM_DEBUG({
+ dbgs() << "\t\t[Def] OpIdx=" << Write.OpIndex
+ << ", PhysReg=" << MRI.getName(Write.RegisterID)
+ << ", Latency=" << Write.Latency
+ << ", WriteResourceID=" << Write.SClassOrWriteResourceID << '\n';
+ });
}
if (MCDesc.hasOptionalDef()) {
Read.OpIndex = i + CurrentUse;
Read.UseIndex = CurrentUse;
Read.SchedClassID = SchedClassID;
- LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Read.OpIndex);
+ LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex
+ << ", UseIndex=" << Read.UseIndex << '\n');
}
for (unsigned CurrentUse = 0; CurrentUse < NumImplicitUses; ++CurrentUse) {
Read.UseIndex = NumExplicitUses + CurrentUse;
Read.RegisterID = MCDesc.getImplicitUses()[CurrentUse];
Read.SchedClassID = SchedClassID;
- LLVM_DEBUG(dbgs() << "\t\tOpIdx=" << Read.OpIndex
- << ", RegisterID=" << Read.RegisterID << '\n');
+ LLVM_DEBUG(dbgs() << "\t\t[Use] OpIdx=" << Read.OpIndex << ", RegisterID="
+ << MRI.getName(Read.RegisterID) << '\n');
}
}
LLVM_DEBUG({
for (const WriteRef &WR : Writes) {
const WriteState &WS = *WR.getWriteState();
- dbgs() << "Found a dependent use of Register "
+ dbgs() << "[PRF] Found a dependent use of Register "
<< MRI.getName(WS.getRegisterID()) << " (defined by intruction #"
<< WR.getSourceIndex() << ")\n";
}
}
void RetireStage::notifyInstructionRetired(const InstRef &IR) {
- LLVM_DEBUG(dbgs() << "[E] Instruction Retired: " << IR << '\n');
+ LLVM_DEBUG(dbgs() << "[E] Instruction Retired: #" << IR << '\n');
SmallVector<unsigned, 4> FreedRegs(PRF.getNumRegisterFiles());
const InstrDesc &Desc = IR.getInstruction()->getDesc();
++I;
IssuedQueue.erase(ToRemove);
} else {
- LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction " << Entry.first
+ LLVM_DEBUG(dbgs() << "[SCHEDULER]: Instruction #" << Entry.first
<< " is still executing.\n");
++I;
}
// If necessary, reserve queue entries in the load-store unit (LSU).
const bool Reserved = LSU->reserve(IR);
if (!IR.getInstruction()->isReady() || (Reserved && !LSU->isReady(IR))) {
- LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding " << IR << " to the Wait Queue\n");
+ LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR << " to the Wait Queue\n");
WaitQueue[IR.getSourceIndex()] = IR.getInstruction();
return false;
}
bool Scheduler::issueImmediately(InstRef &IR) {
const InstrDesc &Desc = IR.getInstruction()->getDesc();
if (!Desc.isZeroLatency() && !Resources->mustIssueImmediately(Desc)) {
- LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding " << IR
+ LLVM_DEBUG(dbgs() << "[SCHEDULER] Adding #" << IR
<< " to the Ready Queue\n");
ReadyQueue[IR.getSourceIndex()] = IR.getInstruction();
return false;