message("* vm/common_vm")
-SET(THIS_LIB_VERSION 2.11.1)
+SET(THIS_LIB_VERSION 2.12.0)
#include(cotire)
set(s_vm_common_vm_srcs
#define MAX_OUTPUT 16
// common signal id
-#define SIG_CPU_IRQ 101
-#define SIG_CPU_FIRQ 102
-#define SIG_CPU_NMI 103
-#define SIG_CPU_BUSREQ 104
-#define SIG_CPU_HALTREQ 105
-#define SIG_CPU_DEBUG 106
+#define SIG_CPU_IRQ 101
+#define SIG_CPU_FIRQ 102
+#define SIG_CPU_NMI 103
+#define SIG_CPU_BUSREQ 104
+#define SIG_CPU_HALTREQ 105
+#define SIG_CPU_DEBUG 106
+#define SIG_CPU_ADDRESS_DIRTY 107
#define SIG_PRINTER_DATA 201
#define SIG_PRINTER_STROBE 202
virtual void notify_intr_ei() {}
// dma
- virtual void do_dma() {}
+ virtual void do_dma() { }
// cpu
virtual int run(int clock)
}
if((channel_control[ch] & 0x01) == 0) {
data_reg[ch] = src[ch]->read_io8(fixed_addr[ch]) & 0xff;
+ // ToDo: Dirty Memory.
dest[ch]->write_dma_io8((uint32_t)addr_reg[ch] + addr_offset, data_reg[ch]);
} else {
data_reg[ch] = dest[ch]->read_dma_io8((uint32_t)addr_reg[ch] + addr_offset) & 0xff;
// io -> memory
tmp = read_io(ch);
write_mem(dma[ch].areg | (dma[ch].bankreg << 16), tmp);
+ write_signals(&outputs_wrote_mem, dma[ch].areg | (dma[ch].bankreg << 16));
break;
case 0x08:
// memory -> io
// output tc signals
outputs_t outputs_tc;
} dma[4];
+ outputs_t outputs_wrote_mem;
bool low_high;
uint8_t cmd;
dma[i].bankreg = dma[i].incmask = 0;
initialize_output_signals(&dma[i].outputs_tc);
}
+ initialize_output_signals(&outputs_wrote_mem);
mode_word = false;
addr_mask = 0xffffffff;
d_debugger = NULL;
{
register_output_signal(&dma[3].outputs_tc, device, id, mask);
}
+ void set_context_wrote_mem(DEVICE* device, int id)
+ {
+ register_output_signal(&outputs_wrote_mem, device, id, 1);
+ }
void set_mode_word(bool val)
{
mode_word = val;
// io -> memory
uint32_t val;
val = dma[c].dev->read_dma_io16(0);
+ write_signals(&outputs_wrote_mem_word, dma[c].areg);
if(_USE_DEBUGGER) {
if(d_debugger != NULL && d_debugger->now_device_debugging) {
d_debugger->write_via_debugger_data16(dma[c].areg, val);
// io -> memory
uint32_t val;
val = dma[c].dev->read_dma_io8(0);
+ write_signals(&outputs_wrote_mem_byte, dma[c].areg);
if(_USE_DEBUGGER) {
if(d_debugger != NULL && d_debugger->now_device_debugging) {
d_debugger->write_via_debugger_data8(dma[c].areg, val);
//#endif
DEBUGGER *d_debugger;
outputs_t outputs_tc;
+ outputs_t outputs_wrote_mem_byte;
+ outputs_t outputs_wrote_mem_word;
struct {
DEVICE* dev;
_SINGLE_MODE_DMA = false;
_USE_DEBUGGER = false;
initialize_output_signals(&outputs_tc);
+ initialize_output_signals(&outputs_wrote_mem_word);
+ initialize_output_signals(&outputs_wrote_mem_byte);
set_device_name(_T("uPD71071 DMAC"));
}
~UPD71071() {}
{
register_output_signal(&outputs_tc, device, id, mask);
}
+ void set_context_wrote_mem(DEVICE* device, int id)
+ {
+ register_output_signal(&outputs_wrote_mem_byte, device, id, 1);
+ register_output_signal(&outputs_wrote_mem_word, device, id, 2);
+ }
};
#endif
//#ifdef DMA_DEBUG
if(_DMA_DEBUG) this->out_debug_log(_T("RAM[%4x]\n"), addr_b);
//#endif
+ write_signals(&outputs_wrote_mem, addr_b);
write_memory(addr_b, data, &wait_w);
} else {
//#ifdef DMA_DEBUG
//#ifdef DMA_DEBUG
if(_DMA_DEBUG) this->out_debug_log(_T("RAM[%4x]\n"), addr_a);
//#endif
+ write_signals(&outputs_wrote_mem, addr_a);
write_memory(addr_a, data, &wait_w);
} else {
//#ifdef DMA_DEBUG
private:
DEVICE *d_mem, *d_io;
DEBUGGER *d_debugger;
-
+ outputs_t outputs_wrote_mem;
typedef union {
uint16_t m[7][8];
uint16_t t[6*8+1+1];
_SINGLE_MODE_DMA = _DMA_DEBUG = false;
d_cpu = d_child = NULL;
d_debugger = NULL;
+ initialize_output_signals(&outputs_wrote_mem);
set_device_name(_T("Z80 DMA"));
}
~Z80DMA() {}
{
d_debugger = device;
}
+ void set_context_wrote_mem(DEVICE* device, int id)
+ {
+ register_output_signal(&outputs_wrote_mem, device, id, 1);
+ }
};
#endif