arm64: dts: qcom: sm6115: Add mdss/dpu node

Add mdss and dpu node to enable display support on SM6115.

Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221130200950.144618-9-a39.skl@gmail.com

diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi
index fde87d9..c476b5e 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6115.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi
@@ -726,13 +726,196 @@
                        };
                };
 
+               mdss: display-subsystem@5e00000 {
+                       compatible = "qcom,sm6115-mdss";
+                       reg = <0x05e00000 0x1000>;
+                       reg-names = "mdss";
+
+                       power-domains = <&dispcc MDSS_GDSC>;
+
+                       clocks = <&gcc GCC_DISP_AHB_CLK>,
+                                <&gcc GCC_DISP_HF_AXI_CLK>,
+                                <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+                       interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #interrupt-cells = <1>;
+
+                       iommus = <&apps_smmu 0x420 0x2>,
+                                <&apps_smmu 0x421 0x0>;
+
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges;
+
+                       status = "disabled";
+
+                       mdp: display-controller@5e01000 {
+                               compatible = "qcom,sm6115-dpu";
+                               reg = <0x05e01000 0x8f000>,
+                                     <0x05eb0000 0x2008>;
+                               reg-names = "mdp", "vbif";
+
+                               clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&dispcc DISP_CC_MDSS_MDP_CLK>,
+                                        <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+                                        <&dispcc DISP_CC_MDSS_ROT_CLK>,
+                                        <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+                               clock-names = "bus",
+                                             "iface",
+                                             "core",
+                                             "lut",
+                                             "rot",
+                                             "vsync";
+
+                               operating-points-v2 = <&mdp_opp_table>;
+                               power-domains = <&rpmpd SM6115_VDDCX>;
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <0>;
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               dpu_intf1_out: endpoint {
+                                                       remote-endpoint = <&dsi0_in>;
+                                               };
+                                       };
+                               };
+
+                               mdp_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-19200000 {
+                                               opp-hz = /bits/ 64 <19200000>;
+                                               required-opps = <&rpmpd_opp_min_svs>;
+                                       };
+
+                                       opp-192000000 {
+                                               opp-hz = /bits/ 64 <192000000>;
+                                               required-opps = <&rpmpd_opp_low_svs>;
+                                       };
+
+                                       opp-256000000 {
+                                               opp-hz = /bits/ 64 <256000000>;
+                                               required-opps = <&rpmpd_opp_svs>;
+                                       };
+
+                                       opp-307200000 {
+                                               opp-hz = /bits/ 64 <307200000>;
+                                               required-opps = <&rpmpd_opp_svs_plus>;
+                                       };
+
+                                       opp-384000000 {
+                                               opp-hz = /bits/ 64 <384000000>;
+                                               required-opps = <&rpmpd_opp_nom>;
+                                       };
+                               };
+                       };
+
+                       dsi0: dsi@5e94000 {
+                               compatible = "qcom,dsi-ctrl-6g-qcm2290";
+                               reg = <0x05e94000 0x400>;
+                               reg-names = "dsi_ctrl";
+
+                               interrupt-parent = <&mdss>;
+                               interrupts = <4>;
+
+                               clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
+                                        <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_ESC0_CLK>,
+                                        <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&gcc GCC_DISP_HF_AXI_CLK>;
+                               clock-names = "byte",
+                                             "byte_intf",
+                                             "pixel",
+                                             "core",
+                                             "iface",
+                                             "bus";
+
+                               assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
+                                                 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
+                               assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
+
+                               operating-points-v2 = <&dsi_opp_table>;
+                               power-domains = <&rpmpd SM6115_VDDCX>;
+                               phys = <&dsi0_phy>;
+
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               status = "disabled";
+
+                               ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       port@0 {
+                                               reg = <0>;
+                                               dsi0_in: endpoint {
+                                                       remote-endpoint = <&dpu_intf1_out>;
+                                               };
+                                       };
+
+                                       port@1 {
+                                               reg = <1>;
+                                               dsi0_out: endpoint {
+                                               };
+                                       };
+                               };
+
+                               dsi_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       opp-19200000 {
+                                               opp-hz = /bits/ 64 <19200000>;
+                                               required-opps = <&rpmpd_opp_min_svs>;
+                                       };
+
+                                       opp-164000000 {
+                                               opp-hz = /bits/ 64 <164000000>;
+                                               required-opps = <&rpmpd_opp_low_svs>;
+                                       };
+
+                                       opp-187500000 {
+                                               opp-hz = /bits/ 64 <187500000>;
+                                               required-opps = <&rpmpd_opp_svs>;
+                                       };
+                               };
+                       };
+
+                       dsi0_phy: phy@5e94400 {
+                               compatible = "qcom,dsi-phy-14nm-2290";
+                               reg = <0x05e94400 0x100>,
+                                     <0x05e94500 0x300>,
+                                     <0x05e94800 0x188>;
+                               reg-names = "dsi_phy",
+                                           "dsi_phy_lane",
+                                           "dsi_pll";
+
+                               #clock-cells = <1>;
+                               #phy-cells = <0>;
+
+                               clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+                                        <&rpmcc RPM_SMD_XO_CLK_SRC>;
+                               clock-names = "iface", "ref";
+
+                               status = "disabled";
+                       };
+               };
+
                dispcc: clock-controller@5f00000 {
                        compatible = "qcom,sm6115-dispcc";
                        reg = <0x05f00000 0x20000>;
                        clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
                                 <&sleep_clk>,
-                                <0>,
-                                <0>,
+                                <&dsi0_phy 0>,
+                                <&dsi0_phy 1>,
                                 <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
                        #clock-cells = <1>;
                        #reset-cells = <1>;