usbMsgPtr = data;
return 4;
case REQUEST_PHI2_INIT:
+ flash_both_idle();
phi2_init();
return 0;
case REQUEST_CPU_READ:
case REQUEST_PPU_FLASH_ERASE:
flash_ppu_erase(rq->wValue.word);
return 0;
+ case REQUEST_VRAM_CONNECTION:
+ status[0] = vram_connection_get();
+ usbMsgPtr = status;
+ return 1;
}
return 0;
}
#include <util/delay.h>
#include <avr/io.h>
+#include "type.h"
#include "bus_access.h"
//avr/io.h use many macros, I want use IO access by inline function...
/*PDx: use input, empty pin is output*/
#define USB_MISC_DIR IO_DIRECTION(D)
#define USB_MISC_PULLUP IO_OUT(D)
+#define USB_MISC_IN IO_IN(D)
enum iobit_usb_misc{
USB_DPLUS = 2, CPU_IRQ,
USB_DMINUS, VRAM_A10
// DATABUS_OUT = *data;
data++;
clock_wait(1);
- BUS_CONTROL_OUT = control;
//phi2 down
control &= bit_get_negative(CPU_PHI2);
+ BUS_CONTROL_OUT = control;
if((address & 0x8000) != 0){
control &= bit_get_negative(CPU_ROMCS);
}
- clock_wait(1);
+// clock_wait(1);
BUS_CONTROL_OUT = control;
//bus close
- clock_wait(1);
+// clock_wait(1);
BUS_CONTROL_OUT = BUS_CLOSE;
address += 1;
length--;
}
}
+
+uint8_t vram_connection_get(void)
+{
+ uint8_t ret;
+ uint16_t address = 0x2000;
+ direction_write();
+ address_set(address);
+ ret = bit_get(USB_MISC_IN, VRAM_A10);
+ address += 1 << 10;
+
+ address_set(address);
+ ret |= bit_get(USB_MISC_IN, VRAM_A10) << 1;
+ address += 1 << 10;
+
+ address_set(address);
+ ret |= bit_get(USB_MISC_IN, VRAM_A10) << 2;
+ address += 1 << 10;
+
+ address_set(address);
+ ret |= bit_get(USB_MISC_IN, VRAM_A10) << 3;
+ address += 1 << 10;
+
+ return ret;
+}
};
void cpu_write_flash_order(const struct flash_order *t);
void ppu_write_order(const struct flash_order *t);
+uint8_t vram_connection_get(void);
+
#include <util/delay.h>
static inline void clock_wait(double clock)
{
uint8_t w;
_delay_ms(267 + 5);
- w = bit_set(ACCESS_START) | bit_set(UNKOWN) | bit_set(DIRECTION) | bit_set(MOTOR);
+ w = bit_set(ACCESS_START) | bit_set(UNKOWN) | bit_set(VRAM_MIRRORING) | bit_set(DIRECTION) | bit_set(MOTOR);
cpu_write_6502(DISK_CONTROL, 1, &w);
clock_wait(21 - 1);
//DRQ enable
{
return seqence_ppu.status;
}
+void flash_both_idle(void)
+{
+ seqence_cpu.status = IDLE;
+ seqence_ppu.status = IDLE;
+}
static void config_set(uint16_t c000x, uint16_t c2aaa, uint16_t c5555, uint16_t unit, struct flash_seqence *t)
{
t->command_000x = c000x;
#ifndef _FLASHMEMORY_H_
#define _FLASHMEMORY_H_
+void flash_both_idle(void);
//cpu
uint8_t flash_cpu_status(void);
void flash_cpu_config(uint16_t c000x, uint16_t c2aaa, uint16_t c5555, uint16_t unit);
REQUEST_CPU_FLASH_DEVICE,
REQUEST_PPU_FLASH_STATUS, REQUEST_PPU_FLASH_CONFIG_SET,
REQUEST_PPU_FLASH_PROGRAM, REQUEST_PPU_FLASH_ERASE,
- REQUEST_PPU_FLASH_DEVICE
+ REQUEST_PPU_FLASH_DEVICE,
+ REQUEST_VRAM_CONNECTION
};
enum {
READ_PACKET_SIZE = 0x0200,
--- /dev/null
+#ifndef _TYPE_H_
+#define _TYPE_H_
+static inline uint8_t bit_to_data(uint8_t data, int bit)
+{
+ data &= 1;
+ return data << bit;
+}
+static inline uint8_t bit_get(uint8_t data, int bit)
+{
+ data >>= bit;
+ return data & 1;
+}
+#endif