GC v11_0_1 asic needs to issue the EnableGfxImu message after start IMU.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Tim Huang <Tim.Huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
return ret;
}
+int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev)
+{
+ struct smu_context *smu = adev->powerplay.pp_handle;
+ int ret = -EOPNOTSUPP;
+
+ mutex_lock(&adev->pm.mutex);
+ ret = smu_set_gfx_power_up_by_imu(smu);
+ mutex_unlock(&adev->pm.mutex);
+
+ msleep(10);
+
+ return ret;
+}
+
int amdgpu_dpm_baco_enter(struct amdgpu_device *adev)
{
const struct amd_pm_funcs *pp_funcs = adev->powerplay.pp_funcs;
int amdgpu_dpm_set_mp1_state(struct amdgpu_device *adev,
enum pp_mp1_state mp1_state);
+int amdgpu_dpm_set_gfx_power_up_by_imu(struct amdgpu_device *adev);
+
int amdgpu_dpm_baco_exit(struct amdgpu_device *adev);
int amdgpu_dpm_baco_enter(struct amdgpu_device *adev);
return ret;
}
+int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
+{
+ if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu)
+ return -EOPNOTSUPP;
+
+ return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
+}
+
static u32 smu_get_mclk(void *handle, bool low)
{
struct smu_context *smu = handle;
return smu_bump_power_profile_mode(smu, param, param_size);
}
-
static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
{
struct smu_context *smu = handle;
int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
/**
+ * @set_gfx_power_up_by_imu: Enable GFX engine with IMU
+ */
+ int (*set_gfx_power_up_by_imu)(struct smu_context *smu);
+
+ /**
* @read_sensor: Read data from a sensor.
* &sensor: Sensor to read data from.
* &data: Sensor reading.
int smu_set_soft_freq_range(struct smu_context *smu, enum smu_clk_type clk_type,
uint32_t min, uint32_t max);
+int smu_set_gfx_power_up_by_imu(struct smu_context *smu);
+
int smu_set_ac_dc(struct smu_context *smu);
int smu_allow_xgmi_power_down(struct smu_context *smu, bool en);
int smu_v13_0_baco_exit(struct smu_context *smu);
+int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu);
+
int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long input[],
SMU_BACO_STATE_EXIT);
}
+int smu_v13_0_set_gfx_power_up_by_imu(struct smu_context *smu)
+{
+ uint16_t index;
+
+ index = smu_cmn_to_asic_specific_index(smu, CMN2ASIC_MAPPING_MSG,
+ SMU_MSG_EnableGfxImu);
+
+ return smu_cmn_send_msg_without_waiting(smu, index, 0);
+}
+
int smu_v13_0_od_edit_dpm_table(struct smu_context *smu,
enum PP_OD_DPM_TABLE_COMMAND type,
long input[], uint32_t size)
.force_clk_levels = smu_v13_0_4_force_clk_levels,
.set_performance_level = smu_v13_0_4_set_performance_level,
.set_fine_grain_gfx_freq_parameters = smu_v13_0_4_set_fine_grain_gfx_freq_parameters,
+ .set_gfx_power_up_by_imu = smu_v13_0_set_gfx_power_up_by_imu,
};
void smu_v13_0_4_set_ppt_funcs(struct smu_context *smu)