parisc: Fix pdc_toc_pim_11 and pdc_toc_pim_20 definitions

The definitions for pdc_toc_pim_11 and pdc_toc_pim_20 are wrong since they
include an entry for a hversion field which doesn't exist in the specification.

Fix this and clean up some whitespaces so that the whole file will be in
sync with it's copy in the SeaBIOS-hppa sources.

Signed-off-by: Helge Deller <deller@gmx.de>
Cc: stable@vger.kernel.org # v5.16

diff --git a/arch/parisc/include/uapi/asm/pdc.h b/arch/parisc/include/uapi/asm/pdc.h
index acc633c..e794e14 100644 (file)
--- a/arch/parisc/include/uapi/asm/pdc.h
+++ b/arch/parisc/include/uapi/asm/pdc.h
@@ -4,7 +4,7 @@
 
 /*
  *     PDC return values ...
- *     All PDC calls return a subset of these errors. 
+ *     All PDC calls return a subset of these errors.
  */
 
 #define PDC_WARN                 3     /* Call completed with a warning */
@@ -165,7 +165,7 @@
 #define PDC_PSW_GET_DEFAULTS   1       /* Return defaults              */
 #define PDC_PSW_SET_DEFAULTS   2       /* Set default                  */
 #define PDC_PSW_ENDIAN_BIT     1       /* set for big endian           */
-#define PDC_PSW_WIDE_BIT       2       /* set for wide mode            */ 
+#define PDC_PSW_WIDE_BIT       2       /* set for wide mode            */
 
 #define PDC_SYSTEM_MAP 22              /* find system modules          */
 #define PDC_FIND_MODULE        0
@@ -274,7 +274,7 @@
 #define PDC_PCI_PCI_INT_ROUTE_SIZE     13
 #define PDC_PCI_GET_INT_TBL_SIZE       PDC_PCI_PCI_INT_ROUTE_SIZE
 #define PDC_PCI_PCI_INT_ROUTE          14
-#define PDC_PCI_GET_INT_TBL            PDC_PCI_PCI_INT_ROUTE 
+#define PDC_PCI_GET_INT_TBL            PDC_PCI_PCI_INT_ROUTE
 #define PDC_PCI_READ_MON_TYPE          15
 #define PDC_PCI_WRITE_MON_TYPE         16
 
@@ -345,7 +345,7 @@
 
 /* constants for PDC_CHASSIS */
 #define OSTAT_OFF              0
-#define OSTAT_FLT              1 
+#define OSTAT_FLT              1
 #define OSTAT_TEST             2
 #define OSTAT_INIT             3
 #define OSTAT_SHUT             4
@@ -403,7 +403,7 @@ struct zeropage {
        int     vec_pad1[6];
 
        /* [0x040] reserved processor dependent */
-       int     pad0[112];
+       int     pad0[112];              /* in QEMU pad0[0] holds "SeaBIOS\0" */
 
        /* [0x200] reserved */
        int     pad1[84];
@@ -691,6 +691,22 @@ struct pdc_hpmc_pim_20 { /* PDC_PIM */
        unsigned long long fr[32];
 };
 
+struct pim_cpu_state_cf {
+       union {
+       unsigned int
+               iqv : 1,        /* IIA queue Valid */
+               iqf : 1,        /* IIA queue Failure */
+               ipv : 1,        /* IPRs Valid */
+               grv : 1,        /* GRs Valid */
+               crv : 1,        /* CRs Valid */
+               srv : 1,        /* SRs Valid */
+               trv : 1,        /* CR24 through CR31 valid */
+               pad : 24,       /* reserved */
+               td  : 1;        /* TOC did not cause any damage to the system state */
+       unsigned int val;
+       };
+};
+
 struct pdc_toc_pim_11 {
        unsigned int gr[32];
        unsigned int cr[32];
@@ -698,8 +714,7 @@ struct pdc_toc_pim_11 {
        unsigned int iasq_back;
        unsigned int iaoq_back;
        unsigned int check_type;
-       unsigned int hversion;
-       unsigned int cpu_state;
+       struct pim_cpu_state_cf cpu_state;
 };
 
 struct pdc_toc_pim_20 {
@@ -709,8 +724,7 @@ struct pdc_toc_pim_20 {
        unsigned long long iasq_back;
        unsigned long long iaoq_back;
        unsigned int check_type;
-       unsigned int hversion;
-       unsigned int cpu_state;
+       struct pim_cpu_state_cf cpu_state;
 };
 
 #endif /* !defined(__ASSEMBLY__) */