ダブルバッファ読み込み完了

Change-Id: I12995df139040de8eda044ed5b8ca8dd38fad981

diff --git a/VGADisplay/src/exp_ctrl.nsh b/VGADisplay/src/exp_ctrl.nsh
deleted file mode 100644 (file)
index c42e85a..0000000
--- a/VGADisplay/src/exp_ctrl.nsh
+++ /dev/null
@@ -1,10 +0,0 @@
-declare exp_ctrl {
-       input    i_Radrs[14] ;
-       output   o_Rdata[16] ;
-       func_in  fi_Rd_req( i_Radrs ) ;
-       func_out fo_Rd_ack( o_Rdata ) ;
-       
-       input    i_Wdata[8] ;
-       input    i_Wadrs[14] ;
-       func_in  fi_Wr_req( i_Wadrs, i_Wdata ) ;
-}

diff --git a/VGADisplay/src/exp_ctrl.nsl b/VGADisplay/src/exp_ctrl.nsl
deleted file mode 100644 (file)
index 0727ea4..0000000
--- a/VGADisplay/src/exp_ctrl.nsl
+++ /dev/null
@@ -1,40 +0,0 @@
-/* Expantion Control Module */
-
-#include "vram_ctrl.nsl"
-
-declare exp_ctrl {
-       input    i_Radrs[14] ;
-       output   o_Rdata[16] ;
-       func_in  fi_Rd_req( i_Radrs ) ;
-       func_out fo_Rd_ack( o_Rdata ) ;
-       
-       input    i_Wdata[8] ;
-       input    i_Wadrs[14] ;
-       func_in  fi_Wr_req( i_Wadrs, i_Wdata ) ;
-}
-
-module exp_ctrl {
-       wire w_exp_q[16] ;
-       vram_ctrl u_VRAMC ;
-               
-       w_exp_q = {
-               u_VRAMC.o_Rdata[7], u_VRAMC.o_Rdata[7],
-               u_VRAMC.o_Rdata[6], u_VRAMC.o_Rdata[6],
-               u_VRAMC.o_Rdata[5], u_VRAMC.o_Rdata[5],
-               u_VRAMC.o_Rdata[4], u_VRAMC.o_Rdata[4],
-               u_VRAMC.o_Rdata[3], u_VRAMC.o_Rdata[3],
-               u_VRAMC.o_Rdata[2], u_VRAMC.o_Rdata[2],
-               u_VRAMC.o_Rdata[1], u_VRAMC.o_Rdata[1],
-               u_VRAMC.o_Rdata[0], u_VRAMC.o_Rdata[0]
-       } ;
-       
-       if( u_VRAMC.fo_Rd_ack ) fo_Rd_ack( w_exp_q ) ;
-       
-       func fi_Rd_req {
-                       u_VRAMC.fi_Rd_req( i_Radrs ) ;
-       }
-       
-       func fi_Wr_req {
-               u_VRAMC.fi_Wr_req( i_Wadrs, i_Wdata ) ;
-       }
-}
\ No newline at end of file

diff --git a/VGADisplay/src/vga_gen.nsl b/VGADisplay/src/vga_gen.nsl
index 1d099c4..f36a67e 100644 (file)
--- a/VGADisplay/src/vga_gen.nsl
+++ b/VGADisplay/src/vga_gen.nsl
@@ -7,15 +7,25 @@
 
 #include "vga_ram.nsh" // vga ram module
 
+//#define H_ACT_MAX     10'd640
+//#define H_FRONTP_MAX 10'd656
+//#define H_SYNC_MAX    10'd752
+//#define H_BACKP_MAX   10'd800
+
+//#define V_ACT_MAX     10'd480
+//#define V_FRONTP_MAX 10'd490
+//#define V_SYNC_MAX    10'd492
+//#define V_BACKP_MAX   10'd521
+
 #define H_ACT_MAX       10'd640
-#define H_FRONTP_MAX 10'd656
-#define H_SYNC_MAX      10'd752
-#define H_BACKP_MAX     10'd800
+#define H_FRONTP_MAX 10'd655
+#define H_SYNC_MAX      10'd751
+#define H_BACKP_MAX     10'd799
 
 #define V_ACT_MAX       10'd480
-#define V_FRONTP_MAX 10'd490
-#define V_SYNC_MAX      10'd492
-#define V_BACKP_MAX     10'd521
+#define V_FRONTP_MAX 10'd489
+#define V_SYNC_MAX      10'd491
+#define V_BACKP_MAX     10'd519
 
 #define        VCNT_1SEC       26'd25000000
 
@@ -64,10 +74,39 @@ module vga_gen {
        reg r_led = 0 ;
        reg r_init_flg = 0 ;
        reg r_trg[3] = 0 ;
+       reg r_cnt1[26] = 0, r_cnt2[26] = 0, r_cnt3[26] = 0 ;
+       reg r_buff1 = 0 ;
        
        vga_ram u_FIFO ;
        
        {
+/*
+               if(r_vsync) {
+                       r_cnt1++ ;
+               } else {
+                       r_cnt1 := 0 ;
+                       if(r_cnt1 != 0) _display("V High : %d", r_cnt1) ;
+               }
+
+               if(~r_vsync) {
+                       r_cnt2++ ;
+               } else {
+                       r_cnt2 := 0 ;
+                       if(r_cnt2 != 0) _display("V Low : %d", r_cnt2) ;
+               }
+       
+               r_buff1 := r_hsync ;
+       
+               if(r_vsync) {
+                       if(~r_buff1 & r_hsync) {
+                               r_cnt3++ ;
+                       }
+               } else {
+                       r_cnt3 := 0 ;
+                       if(r_cnt3 != 0) _display("H Total: %d times", r_cnt3) ;
+               }
+*/     
+       
                r_trg := { r_trg[1:0], 0b1 } ;
                if(r_trg == 0b011) fs_initialize() ;
        

diff --git a/VGADisplay/src/vga_ram.v b/VGADisplay/src/vga_ram.v
index 70bef6e..33d9ea6 100644 (file)
--- a/VGADisplay/src/vga_ram.v
+++ b/VGADisplay/src/vga_ram.v
@@ -18,25 +18,31 @@ module vga_ram (
        
        reg [8:0] r_wradrs ;
        reg [8:0] r_rdadrs ;
-       reg r_rdadrs_buff ;
+       reg [8:0] r_rdadrs_buff ;
+       reg r_rdack ;
 
-       (* remstyle = "no_rw_check" *) reg [7:0] mem1[511:0] ;
+       (* remstyle = "no_rw_check" *) reg [8:0] mem1[511:0] ;
 
        assign o_rddata = mem1[r_rdadrs] ;
-       assign o_rdack = (r_rdadrs_buff != r_rdadrs[8]) ;
+       assign o_rdack = r_rdack ;
        
        always @( posedge i_clk50 ) begin
-               r_rdadrs_buff <= r_rdadrs[8] ;
+               r_rdadrs_buff <= r_rdadrs ;
+               if((r_rdadrs_buff == 9'd319) & (r_rdadrs == 9'd0)) r_rdack <= 1 ;
+               else if((r_rdadrs_buff == 9'd159) & (r_rdadrs == 9'd160)) r_rdack <= 1 ;
+               else r_rdack <= 0 ;
        end
        
        // memory read command
        always @ ( posedge i_clk25 or posedge i_rst ) begin
                if(i_rst) begin
                        r_rdadrs <= 0 ;
+                       r_rdadrs_buff <= 0 ;
+                       r_rdack <= 0 ;
                end
                else if( i_re ) begin
-                       if(r_rdadrs < 480)      r_rdadrs <= r_rdadrs + 9'd1 ;
-                       else                            r_rdadrs <= 9'd0 ;
+                       if(r_rdadrs == 9'd319)  r_rdadrs <= 9'd0 ;
+                       else                            r_rdadrs <= r_rdadrs + 9'd1 ;
                end
        end
 
@@ -48,8 +54,8 @@ module vga_ram (
                else if( i_we ) begin
                        mem1[r_wradrs] <= i_wrdata ;
 
-                       if(r_wradrs < 480)      r_wradrs <= r_wradrs + 9'd1 ;
-                       else                            r_wradrs <= 9'd0 ;
+                       if(r_wradrs == 9'd319)  r_wradrs <= 9'd0 ;
+                       else                            r_wradrs <= r_wradrs + 9'd1 ;
                end
        end
 endmodule
\ No newline at end of file

diff --git a/VGADisplay/src/vga_top.nsl b/VGADisplay/src/vga_top.nsl
index cd212fd..dad0b4d 100644 (file)
--- a/VGADisplay/src/vga_top.nsl
+++ b/VGADisplay/src/vga_top.nsl
@@ -7,12 +7,10 @@
 */\r
 \r
 #include "vga_gen.nsl"\r
-#include "exp_ctrl.nsh"\r
+#include "vram.nsl"\r
 //#include "from_ctrl.nsh"\r
 #include "push_sw.nsl"\r
 \r
-#define CNT1S 26'd50000000\r
-\r
 #define CNT1S     26'd50000000 // 1     [s]\r
 #define CNTHS             26'd25000000 // 0.5   [s]\r
 #define CNTQS     26'd12500000 // 0.25  [s]\r
@@ -39,30 +37,18 @@ module vga_top {
        reg r_sec_cnt[26] = 0 ;\r
        reg r_LED = 0 ;\r
        \r
-       reg r_init_cnt[14] = 0 ;\r
-       reg r_vram_adrs1[14] = 0 ;\r
-       reg r_vram_adrs2[14] = 0 ;\r
+       reg r_init_cnt[13] = 0 ;\r
+       reg r_vram_adrs[14] = 0 ;\r
        reg r_vram_rddata[16]  = 0 ;\r
-       reg r_vram_start_adrs[14] = 0 ;\r
-       reg r_hld_vram_start = 0 ;\r
+       reg r_vram_start_adrs[13] = 0 ;\r
+       reg r_fifo_write_adrs = 0 ;\r
        reg r_fifo_rst = 0 ;\r
+       reg r_vga_ack_hld = 0 ;\r
        \r
-       wire w_wrdata1[8] ;\r
-       wire w_wrdata2[8] ;\r
-       wire w_wradrs1[8] ;\r
-       wire w_wradrs2[8] ;\r
-       func_self fs_fifo1_write( w_wradrs1, w_wrdata1 ) ;\r
-       func_self fs_fifo2_write( w_wradrs2, w_wrdata2 ) ;\r
-       \r
+       wire w_data[8], w_exp_data[16] ;\r
+       func_self fs_exp_exec(w_data):w_exp_data ;\r
        func_self fs_init() ;\r
-       \r
-       func_self fs_fifo1_charge() ;\r
-       func_self fs_fifo2_charge() ;\r
-\r
-       func_self fs_vram_cnt_inc ;\r
-       \r
-       reg r_wradrs1[8] = 0 ;\r
-       reg r_wradrs2[8] = 0 ;\r
+       func_self fs_fifo_write() ;\r
        \r
        reg r_out_sel = 0 ;\r
 \r
@@ -74,11 +60,11 @@ module vga_top {
 \r
        vga_gen         u_VGA ;\r
        push_sw         u_BTN[4] ;\r
-//     exp_ctrl        u_EXP ;\r
+       vram            u_VRAM ;\r
 //     from_ctrl       u_FROMC ;\r
        \r
        {\r
-               /* IF */\r
+               /* UI */\r
                u_BTN[0].i_sw = i_sw[0] ;\r
                u_BTN[1].i_sw = i_sw[1] ;\r
                u_BTN[2].i_sw = i_sw[2] ;\r
@@ -103,27 +89,11 @@ module vga_top {
                o_vsync                  = u_VGA.o_vsync ;\r
                o_hsync                  = u_VGA.o_hsync ;\r
                u_VGA.i_clk50    = m_clock ;\r
-               r_hld_vram_start := u_VGA.o_vcnt[0] ;\r
                u_VGA.i_fifo_rst = r_fifo_rst ;\r
-\r
-               \r
                \r
                trigger := { trigger[1:0], 0b1 } ;\r
                if(trigger == 3'b011) fs_init() ;\r
 \r
-\r
-//             if(~r_reset) {\r
-//                     any {\r
-//                             r_hld_vram_start & ~u_VGA.o_vcnt[0] : { //FIFO1\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
-//                                     if(u_VGA.o_vcnt < 10'd480) fs_fifo2_charge() ;\r
-//                             }\r
-//                             ~r_hld_vram_start & u_VGA.o_vcnt[0] : { //FIFO2\82ð\93Ç\82Ý\8fo\82·\83^\83C\83~\83\93\83O\r
-//                                     if(u_VGA.o_vcnt < 10'd480) fs_fifo1_charge() ;\r
-//                             }\r
-//                     }\r
-//             }\r
-\r
-\r
                any {\r
                        r_sec_cnt == CNT1S : {\r
                                r_sec_cnt := 0 ;\r
@@ -134,141 +104,31 @@ module vga_top {
                        }\r
                }\r
 \r
-\r
                r_cnt  := ~r_cnt ;\r
                o_LED   = { 0b00, i_sw, r_LED, u_VGA.o_led } ;\r
 \r
                u_VGA.m_clock = r_cnt ;\r
                u_VGA.p_reset = r_reset ;\r
 \r
-\r
+               r_vga_ack_hld := u_VGA.o_rdack ;\r
+               if(~r_vga_ack_hld & u_VGA.o_rdack) {\r
+                       fs_fifo_write() ;\r
+               }\r
        }\r
        \r
        func fs_init seq {\r
-               /* VRAM\8f\89\8aú\89»\83\8b\81[\83`\83\93 */\r
-//             for(r_init_cnt:=0;r_init_cnt<9600;r_init_cnt++) {\r
-//                     u_EXP.fi_Wr_req(r_init_cnt, r_init_cnt[7:0]) ;\r
-//             }\r
-               \r
-//             for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
-//                     u_EXP.fi_Rd_req(r_vram_adrs1) ;\r
-//                     r_vram_rddata := u_EXP.o_Rdata ;\r
-//                     {\r
-//                             fs_fifo1_write(r_wradrs1, r_vram_rddata[15:8]) ;\r
-//                             r_wradrs1++ ;\r
-//                     }\r
-//                     {\r
-//                             fs_fifo1_write(r_wradrs1, r_vram_rddata[7:0]) ;\r
-//                             r_wradrs1++ ;\r
-//                     }\r
-//                     \r
-//                     r_vram_adrs1++ ;\r
-//             }\r
-               \r
-//             r_wradrs1 := 0 ; //act!!\r
-\r
-               \r
-//             for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
-//                     u_EXP.fi_Rd_req(r_vram_adrs2) ;\r
-//                     r_vram_rddata := u_EXP.o_Rdata ;\r
-//                     {\r
-//                             fs_fifo2_write(r_wradrs2, r_vram_rddata[15:8]) ;\r
-//                             r_wradrs2++ ;\r
-//                     }\r
-//                     {\r
-//                             fs_fifo2_write(r_wradrs2, r_vram_rddata[7:0]) ;\r
-//                             r_wradrs2++ ;\r
-//                     }\r
-//\r
-//                     r_vram_adrs2++ ;\r
-//             }\r
-               \r
-//             r_wradrs2 := 0 ; //ACT!!\r
-\r
-//             r_vram_start_adrs := r_vram_start_adrs + 14'd40 ;\r
-\r
                r_fifo_rst := 1 ;\r
                ;;;\r
                r_fifo_rst := 0 ;\r
                ;;;\r
 \r
-               for(r_init_cnt:=0; r_init_cnt<120; r_init_cnt++ ) {\r
-                       u_VGA.fi_fifo_write(8'hFF) ;\r
-                       u_VGA.fi_fifo_write(8'h00) ;\r
-               }\r
-               for(r_init_cnt:=0; r_init_cnt<120; r_init_cnt++ ) {\r
-                       u_VGA.fi_fifo_write(8'h00) ;\r
-                       u_VGA.fi_fifo_write(8'hFF) ;\r
-               }               \r
+               fs_fifo_write() ;\r
+               p_wait(26'd500) ;\r
+               fs_fifo_write() ;\r
 \r
                r_reset := 0 ;          \r
        }\r
 \r
-/*     \r
-       func fs_fifo1_write {\r
-               u_VGA.fi_fifo1_write(w_wradrs1, w_wrdata1) ;\r
-       }\r
-\r
-       func fs_fifo2_write {\r
-               u_VGA.fi_fifo2_write(w_wradrs2, w_wrdata2) ;    \r
-       }\r
-*/\r
-       \r
-/*\r
-       func fs_fifo1_charge seq {\r
-               for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
-                       u_EXP.fi_Rd_req(r_vram_adrs1) ;\r
-                       r_vram_rddata := u_EXP.o_Rdata ;\r
-                       {\r
-                               fs_fifo1_write(r_wradrs1, r_vram_rddata[7:0]) ;\r
-                               r_wradrs1++ ;\r
-                       }\r
-                       {\r
-                               fs_fifo1_write(r_wradrs1, r_vram_rddata[15:8]) ;\r
-                               r_wradrs1++ ;\r
-                       }\r
-                       \r
-                       r_vram_adrs1++;\r
-               }\r
-               \r
-               r_wradrs1:= 0 ;\r
-               if( r_vram_adrs1 == 14'd9600 ) r_vram_adrs1 := 0 ;\r
-       }\r
-*/\r
-\r
-/*\r
-       func fs_fifo2_charge seq {\r
-\r
-               for(r_init_cnt:=0;r_init_cnt<40;r_init_cnt++) {\r
-                       u_EXP.fi_Rd_req(r_vram_adrs2) ;\r
-                       r_vram_rddata := u_EXP.o_Rdata ;\r
-                       {\r
-                               fs_fifo2_write(r_wradrs2, r_vram_rddata[7:0]) ;\r
-                               r_wradrs2++ ;\r
-                       }\r
-                       {\r
-                               fs_fifo2_write(r_wradrs2, r_vram_rddata[15:8]) ;\r
-                               r_wradrs2++ ;\r
-                       }\r
-                       r_vram_adrs2++ ;\r
-               }\r
-               \r
-               r_wradrs2 := 0 ;\r
-               if( r_vram_adrs2 == 14'd9600 ) r_vram_adrs2 := 0 ;\r
-               \r
-               fs_vram_cnt_inc() ;\r
-       }\r
-\r
-       func fs_vram_cnt_inc {\r
-               any {\r
-                       r_vram_start_adrs == 14'd9560 :\r
-                               r_vram_start_adrs := 0 ;\r
-                       else : {\r
-                               r_vram_start_adrs := r_vram_start_adrs + 14'd40 ;\r
-                       }\r
-               }\r
-       }\r
-*/\r
        \r
        proc p_wait {\r
                any {\r
@@ -281,135 +141,22 @@ module vga_top {
                        }\r
                }               \r
        }\r
+       \r
+       func fs_exp_exec {\r
+               w_exp_data = {\r
+                       w_data[7], w_data[7], w_data[6], w_data[6],\r
+                       w_data[5], w_data[5], w_data[4], w_data[4],\r
+                       w_data[3], w_data[3], w_data[2], w_data[2],\r
+                       w_data[1], w_data[1], w_data[0], w_data[0]\r
+               } ;\r
+       }\r
 \r
-/*     \r
-       func test_write seq {\r
-               p_wait(CNT1S) ;\r
-               p_wait(CNT1S) ;\r
-               p_wait(CNT1S) ;\r
-               p_wait(CNT1S) ;\r
-               p_wait(CNT1S) ;\r
-               u_FROMC.fi_write_word(6'd0,5'd0,8'd87) ; //"W"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd1,5'd0,8'd97) ; //"a"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd2,5'd0,8'd107) ; //"k"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd3,5'd0,8'd101) ; //"e"\r
-               p_wait(CNTHS) ;\r
-\r
-               u_FROMC.fi_write_word(6'd5,5'd0,8'd117) ; //"u"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd6,5'd0,8'd112) ; //"p"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd7,5'd0,8'd44) ; //","\r
-               p_wait(CNTHS) ;\r
-\r
-               u_FROMC.fi_write_word(6'd9,5'd0,8'd78) ; //"N"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd10,5'd0,8'd101) ; //"e"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd11,5'd0,8'd111) ; //"o"\r
-               p_wait(CNTHS) ;\r
-\r
-               u_FROMC.fi_write_word(6'd12,5'd0,8'd46) ; //"."\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd13,5'd0,8'd46) ; //"."\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd14,5'd0,8'd46) ; //"."\r
-               p_wait(CNTHS) ;\r
-\r
-               p_wait(CNT1S) ;\r
-               p_wait(CNT1S) ;\r
-\r
-               u_FROMC.fi_write_word(6'd0,5'd1,8'd84) ; //"T"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd1,5'd1,8'd104) ; //"h"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd2,5'd1,8'd101) ; //"e"\r
-               p_wait(CNTHS) ;\r
-\r
-               u_FROMC.fi_write_word(6'd4,5'd1,8'd77) ; //"M"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd5,5'd1,8'd97) ; //"a"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd6,5'd1,8'd116) ; //"t"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd7,5'd1,8'd114) ; //"r"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd8,5'd1,8'd105) ; //"i"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd9,5'd1,8'd120) ; //"x"\r
-               p_wait(CNTHS) ;\r
-\r
-               u_FROMC.fi_write_word(6'd11,5'd1,8'd104) ; //"h"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd12,5'd1,8'd97) ; //"a"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd13,5'd1,8'd115) ; //"s"\r
-               p_wait(CNTHS) ;\r
-\r
-               u_FROMC.fi_write_word(6'd15,5'd1,8'd121) ; //"y"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd16,5'd1,8'd111) ; //"o"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd17,5'd1,8'd117) ; //"u"\r
-               p_wait(CNTHS) ;\r
+       func fs_fifo_write seq {\r
+               for(r_init_cnt:=0; r_init_cnt<80; r_init_cnt++) {\r
+                       u_VGA.fi_fifo_write( 8#r_fifo_write_adrs );\r
+                       u_VGA.fi_fifo_write( ~(8#r_fifo_write_adrs) );\r
+               }\r
                \r
-               u_FROMC.fi_write_word(6'd18,5'd1,8'd46) ; //"."\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd19,5'd1,8'd46) ; //"."\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd20,5'd1,8'd46) ; //"."\r
-               p_wait(CNTHS) ;\r
-\r
-               p_wait(CNT1S) ;\r
-               p_wait(CNT1S) ;\r
-\r
-               u_FROMC.fi_write_word(6'd0,5'd2,8'd70) ; //"F"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd1,5'd2,8'd111) ; //"o"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd2,5'd2,8'd108) ; //"l"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd3,5'd2,8'd108) ; //"l"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd4,5'd2,8'd111) ; //"o"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd5,5'd2,8'd119) ; //"w"\r
-               p_wait(CNTHS) ;\r
-\r
-               u_FROMC.fi_write_word(6'd7,5'd2,8'd116) ; //"t"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd8,5'd2,8'd104) ; //"h"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd9,5'd2,8'd101) ; //"e"\r
-               p_wait(CNTHS) ;\r
-\r
-               u_FROMC.fi_write_word(6'd10,5'd2,8'd119) ; //"w"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd11,5'd2,8'd104) ; //"h"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd12,5'd2,8'd105) ; //"i"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd13,5'd2,8'd116) ; //"t"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd14,5'd2,8'd101) ; //"e"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd16,5'd2,8'd114) ; //"r"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd17,5'd2,8'd97) ; //"a"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd18,5'd2,8'd98) ; //"b"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd19,5'd2,8'd98) ; //"b"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd20,5'd2,8'd105) ; //"i"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd21,5'd2,8'd116) ; //"t"\r
-               p_wait(CNTHS) ;\r
-               u_FROMC.fi_write_word(6'd22,5'd2,8'd46) ; //"."\r
-               p_wait(CNTHS) ;\r
+               r_fifo_write_adrs := ~r_fifo_write_adrs ;\r
        }\r
-*/\r
 }
\ No newline at end of file

diff --git a/VGADisplay/src/vram.nsh b/VGADisplay/src/vram.nsh
index 11077aa..a3828a9 100644 (file)
--- a/VGADisplay/src/vram.nsh
+++ b/VGADisplay/src/vram.nsh
@@ -8,8 +8,8 @@
 declare vram {
        input  clock ;
        input  data[8] ;
-       input  rdaddress[14] ;
-       input  wraddress[14] ;
+       input  rdaddress[13] ;
+       input  wraddress[13] ;
        input  wren ;
        output q[8] ;
 }
\ No newline at end of file

diff --git a/VGADisplay/src/vram.nsl b/VGADisplay/src/vram.nsl
index 068b94b..dc7bde4 100644 (file)
--- a/VGADisplay/src/vram.nsl
+++ b/VGADisplay/src/vram.nsl
@@ -3,14 +3,14 @@
 declare vram {
        input  clock ;
        input  data[8] ;
-       input  rdaddress[14] ;
-       input  wraddress[14] ;
+       input  rdaddress[13] ;
+       input  wraddress[13] ;
        input  wren ;
        output q[8] ;
 }
 
 module vram {
-       mem m_vram[16384][8] ;
+       mem m_vram[8192][8] ;
        reg r_ram_data[8] = 0 ;
        
        {

diff --git a/VGADisplay/src/vram_ctrl.nsl b/VGADisplay/src/vram_ctrl.nsl
index 48dc7a2..74104b7 100644 (file)
--- a/VGADisplay/src/vram_ctrl.nsl
+++ b/VGADisplay/src/vram_ctrl.nsl
@@ -11,8 +11,8 @@
 declare vram_ctrl {
 
        input    i_Wdata[8] ;   // in Write Data
-       input    i_Wadrs[14] ;  // in Write Address
-       input    i_Radrs[14] ;  // in Read Address
+       input    i_Wadrs[13] ;  // in Write Address
+       input    i_Radrs[13] ;  // in Read Address
        output   o_Rdata[8] ;   // out Read Data
 
        func_in  fi_Wr_req( i_Wadrs, i_Wdata ) ;
@@ -22,7 +22,7 @@ declare vram_ctrl {
 module vram_ctrl{
        vram u_VRAM ;
        
-       reg r_Radrs_hld[14] = 0 ;
+       reg r_Radrs_hld[13] = 0 ;
 
        {
                u_VRAM.clock = m_clock ;