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drm/i915/tgl: Make sure FBs have a correct CCS plane stride
authorImre Deak <imre.deak@intel.com>
Sat, 21 Dec 2019 12:05:40 +0000 (14:05 +0200)
committerImre Deak <imre.deak@intel.com>
Mon, 23 Dec 2019 11:51:00 +0000 (13:51 +0200)
The CCS plane stride must be fixed on TGL, as it's not configurable for
the display. Instead the HW has a hardwired logic to determine it from
the main plane stride. Make sure userspace passes in the correct stride.

Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20191221120543.22816-8-imre.deak@intel.com
drivers/gpu/drm/i915/display/intel_display.c

index ae28589..7e55829 100644 (file)
@@ -2621,6 +2621,12 @@ bool is_ccs_modifier(u64 modifier)
               modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
 }
 
+static int gen12_ccs_aux_stride(struct drm_framebuffer *fb, int ccs_plane)
+{
+       return DIV_ROUND_UP(fb->pitches[ccs_to_main_plane(fb, ccs_plane)],
+                           512) * 64;
+}
+
 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
                              u32 pixel_format, u64 modifier)
 {
@@ -16550,6 +16556,17 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
                        goto err;
                }
 
+               if (is_gen12_ccs_plane(fb, i)) {
+                       int ccs_aux_stride = gen12_ccs_aux_stride(fb, i);
+
+                       if (fb->pitches[i] != ccs_aux_stride) {
+                               DRM_DEBUG_KMS("ccs aux plane %d pitch (%d) must be %d\n",
+                                             i,
+                                             fb->pitches[i], ccs_aux_stride);
+                               goto err;
+                       }
+               }
+
                fb->obj[i] = &obj->base;
        }