// If we have at least one (non-frame-index, non-RIP) register operand,
// and neither operand is load-dependent, we need to check the load.
+ // Also handle explicit references to RSP as used by idempotent atomic
+ // or with 0.
unsigned BaseReg = 0, IndexReg = 0;
if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP &&
- BaseMO.getReg() != X86::NoRegister)
+ BaseMO.getReg() != X86::RSP && BaseMO.getReg() != X86::NoRegister)
BaseReg = BaseMO.getReg();
if (IndexMO.getReg() != X86::NoRegister)
IndexReg = IndexMO.getReg();
call void @sink(i32 %e7)
ret void
}
+
+; Make sure we don't crash on idempotent atomic operations which have a
+; hardcoded reference to RSP+offset.
+define void @idempotent_atomic(i32* %x) speculative_load_hardening {
+; X64-LABEL: idempotent_atomic:
+; X64: # %bb.0:
+; X64-NEXT: movq %rsp, %rax
+; X64-NEXT: movq $-1, %rcx
+; X64-NEXT: sarq $63, %rax
+; X64-NEXT: lock orl $0, (%rsp)
+; X64-NEXT: shlq $47, %rax
+; X64-NEXT: orq %rax, %rsp
+; X64-NEXT: retq
+;
+; X64-LFENCE-LABEL: idempotent_atomic:
+; X64-LFENCE: # %bb.0:
+; X64-LFENCE-NEXT: lock orl $0, (%rsp)
+; X64-LFENCE-NEXT: retq
+ %tmp = atomicrmw or i32* %x, i32 0 seq_cst
+ ret void
+}