drm/i915/gvt: Enable virtual display support for BXT.

Virtual monitor on BXT start from port B.
Unlike SKL/KBL, digital display port connectivity is detected via
GEN8_DE_PORT_ISR so emulate monitor state change by setting it.

Signed-off-by: Colin Xu <colin.xu@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c
index 38521fa..6ee50cb 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/display.c
+++ b/drivers/gpu/drm/i915/gvt/display.c
@@ -171,6 +171,29 @@ static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
        struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
        int pipe;
 
+       if (IS_BROXTON(dev_priv)) {
+               vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
+                       BXT_DE_PORT_HP_DDIB |
+                       BXT_DE_PORT_HP_DDIC);
+
+               if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
+                       vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
+                               BXT_DE_PORT_HP_DDIA;
+               }
+
+               if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
+                       vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
+                               BXT_DE_PORT_HP_DDIB;
+               }
+
+               if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
+                       vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
+                               BXT_DE_PORT_HP_DDIC;
+               }
+
+               return;
+       }
+
        vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTB_HOTPLUG_CPT |
                        SDE_PORTC_HOTPLUG_CPT |
                        SDE_PORTD_HOTPLUG_CPT);

diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index f613376..4b98539 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -77,6 +77,20 @@ static unsigned char edid_get_byte(struct intel_vgpu *vgpu)
        return chr;
 }
 
+static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
+{
+       int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
+       int port = -EINVAL;
+
+       if (port_select == 1)
+               port = PORT_B;
+       else if (port_select == 2)
+               port = PORT_C;
+       else if (port_select == 3)
+               port = PORT_D;
+       return port;
+}
+
 static inline int get_port_from_gmbus0(u32 gmbus0)
 {
        int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
@@ -105,6 +119,7 @@ static void reset_gmbus_controller(struct intel_vgpu *vgpu)
 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
                        unsigned int offset, void *p_data, unsigned int bytes)
 {
+       struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
        int port, pin_select;
 
        memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
@@ -116,7 +131,10 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
        if (pin_select == 0)
                return 0;
 
-       port = get_port_from_gmbus0(pin_select);
+       if (IS_BROXTON(dev_priv))
+               port = bxt_get_port_from_gmbus0(pin_select);
+       else
+               port = get_port_from_gmbus0(pin_select);
        if (WARN_ON(port < 0))
                return 0;