int last_cpu;
int output; /* IRQ level, e.g. OPENPIC_OUTPUT_INT */
int pending; /* TRUE if IRQ is pending */
+ bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
} IRQSource;
#define IVPR_MASK_SHIFT 31
DPRINTF("%s: IRQ %d is not pending\n", __func__, n_IRQ);
return;
}
- if (src->ivpr & IVPR_MASK_MASK) {
+ if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
/* Interrupt source is disabled */
DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
return;
}
src->output = OPENPIC_OUTPUT_CINT;
+ src->nomask = true;
src->destmask = 0;
for (i = 0; i < opp->nb_cpus; i++) {
}
} else {
src->output = OPENPIC_OUTPUT_INT;
+ src->nomask = false;
src->destmask = src->idr & normal_mask;
}
} else {