case 0x08:
case 0x09:
cmd = data & 0xffff;
- if(((data & 0x04) != (cmd & 0x04)) && (selch == 3)) {
- if((data & 0x04) == 0) {
- out_debug_log(_T("TRANSFER: CMD=%04X -> %04X CH=%d\nADDR=%08X"), cmd, (cmd & 0xff00) | (data & 0xff), selch, dma[selch].areg);
- }
- }
+// if(((data & 0x04) != (cmd & 0x04)) && (selch == 3)) {
+// if((data & 0x04) == 0) {
+// out_debug_log(_T("TRANSFER: CMD=%04X -> %04X CH=%d\nADDR=%08X"), cmd, (cmd & 0xff00) | (data & 0xff), selch, dma[selch].areg);
+// }
+// }
break;
default:
// write_io8(addr & 0x0e, data);
return;
break;
case 0x08:
- if(((data & 0x04) != (cmd & 0x04)) && (selch == 3)) {
- if((data & 0x04) != 0) break;
- out_debug_log(_T("TRANSFER: CMD=%04X -> %04X CH=%d\nADDR=%08X"), cmd, (cmd & 0xff00) | (data & 0xff), selch, dma[selch].areg);
- }
+// if(((data & 0x04) != (cmd & 0x04)) && (selch == 3)) {
+// if((data & 0x04) != 0) break;
+// out_debug_log(_T("TRANSFER: CMD=%04X -> %04X CH=%d\nADDR=%08X"), cmd, (cmd & 0xff00) | (data & 0xff), selch, dma[selch].areg);
+// }
break;
case 0x0a:
- if((selch == 3)) {
- out_debug_log(_T("SET MODE[%d] to %02X"), selch, data);
- }
+// if((selch == 3)) {
+// out_debug_log(_T("SET MODE[%d] to %02X"), selch, data);
+// }
break;
case 0x0e:
if(((data | req) & 0x08) != 0) {
{
if(dma[c].creg == 0) { // OK?
// TC
- if(c == 3) {
- out_debug_log(_T("TRANSFER COMPLETED CH.3: AREG=%08X BAREG=%08X CREG=%08X BCREG=%08X"),
- (dma[c].areg & 0xffffffff) ,
- (dma[c].bareg & 0xffffffff) ,
- dma[c].creg & 0x00ffffff,
- dma[c].bcreg & 0x00ffffff
- );
-
- }
+// if(c == 3) {
+// out_debug_log(_T("TRANSFER COMPLETED CH.3: AREG=%08X BAREG=%08X CREG=%08X BCREG=%08X"),
+// (dma[c].areg & 0xffffffff) ,
+// (dma[c].bareg & 0xffffffff) ,
+// dma[c].creg & 0x00ffffff,
+// dma[c].bcreg & 0x00ffffff
+// );
+//
+// }
}
return UPD71071::do_dma_epilogue(c);
}