[Hexagon] Updating inline saturate lanes for v62 version.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@297920 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
index 8c93915..853f762 100644 (file)
--- a/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
+++ b/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
@@ -105,7 +105,10 @@ void HexagonCVIResource::SetupTUL(TypeUnitsAndLanes *TUL, StringRef CPU) {
   (*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1);
   (*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2);
   (*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1);
-  (*TUL)[HexagonII::TypeCVI_VINLANESAT] = UnitsAndLanes(CVI_SHIFT, 1);
+  (*TUL)[HexagonII::TypeCVI_VINLANESAT] =
+      (CPU == "hexagonv60" || CPU == "hexagonv61" || CPU == "hexagonv61v1") ?
+      UnitsAndLanes(CVI_SHIFT, 1) :
+      UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
   (*TUL)[HexagonII::TypeCVI_VM_LD] =
       UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
   (*TUL)[HexagonII::TypeCVI_VM_TMP_LD] = UnitsAndLanes(CVI_NONE, 0);

diff --git a/test/MC/Hexagon/bug20416.s b/test/MC/Hexagon/bug20416.s
new file mode 100644 (file)
index 0000000..e4fb194
--- /dev/null
+++ b/test/MC/Hexagon/bug20416.s
@@ -0,0 +1,13 @@
+# RUN: not llvm-mc -mv60 -mhvx -filetype=asm %s 2>%t; FileCheck %s --check-prefix=CHECK-V60-ERROR <%t
+# RUN:     llvm-mc -mv62 -mhvx -filetype=asm %s | FileCheck %s
+
+// for this a v60+/hvx instruction sequence, make sure fails with v60
+// but passes with v62.  this is because this instruction uses different
+// itinerary between v60 and v62
+{
+  v0.h=vsat(v5.w,v9.w)
+  v16.h=vsat(v6.w,v26.w)
+}
+# CHECK-V60-ERROR: rror: invalid instruction packet: slot error
+# CHECK: v0.h = vsat(v5.w,v9.w)
+# CHECK: v16.h = vsat(v6.w,v26.w)