Merge patch series "target/riscv: Various fixes to gdbstub and CSR access"

Bin Meng <bmeng@tinylab.org> says:

At present gdbstub reports an incorrect / incomplete CSR list in the
target description XML, for example:

- menvcfg is reported in 'sifive_u' machine
- fcsr is missing in a F/D enabled processor

The issue is caused by:
- priv spec version check is missing when reporting CSRs
- CSR predicate() routine is called without turning on the debugger flag

* b4-shazam-merge:
  target/riscv: Group all predicate() routines together
  target/riscv: Drop priv level check in mseccfg predicate()
  target/riscv: Allow debugger to access sstc CSRs
  target/riscv: Allow debugger to access {h, s}stateen CSRs
  target/riscv: Allow debugger to access seed CSR
  target/riscv: Allow debugger to access user timer and counter CSRs
  target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml
  target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()
  target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64
  target/riscv: Simplify getting RISCVCPU pointer from env
  target/riscv: Simplify {read, write}_pmpcfg() a little bit
  target/riscv: Use 'bool' type for read_only
  target/riscv: Coding style fixes in csr.c
  target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled
  target/riscv: gdbstub: Minor change for better readability
  target/riscv: Use g_assert() for the predicate() NULL check
  target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()
  target/riscv: gdbstub: Check priv spec version before reporting CSR

Message-ID: <20230228104035.1879882-1-bmeng@tinylab.org>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --cc target/riscv/csr.c
index a1ecf62,3a7e021..a2cf353
--- 1/target/riscv/csr.c
--- 2/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@@ -90,10 -53,10 +53,9 @@@ static RISCVException fs(CPURISCVState 
  
  static RISCVException vs(CPURISCVState *env, int csrno)
  {
-     CPUState *cs = env_cpu(env);
-     RISCVCPU *cpu = RISCV_CPU(cs);
+     RISCVCPU *cpu = env_archcpu(env);
  
 -    if (env->misa_ext & RVV ||
 -        cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
 +    if (cpu->cfg.ext_zve32f) {
  #if !defined(CONFIG_USER_ONLY)
          if (!env->debugger && !riscv_cpu_vector_enabled(env)) {
              return RISCV_EXCP_ILLEGAL_INST;