+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
+ * archures.c (bfd_mach_fr450): New.
+ * bfd-in2.h: Regenerate.
+ * cpu-frv.c (arch_info_450): New bfd_arch_info_type.
+ (arch_info_500): Link to it.
+ * elf32-frv.c (elf32_frv_machine, frv_elf_merge_private_bfd_data)
+ (frv_elf_print_private_bfd_data): Handle fr405 and fr450 header flags.
+ (frv_elf_arch_extension_p): New function.
+ (frv_elf_merge_private_bfd_data): Use it.
+
2004-02-28 H.J. Lu <hongjiu.lu@intel.com>
* elf-bfd.h (_bfd_elf_link_add_archive_symbols): New prototype.
.#define bfd_mach_frvsimple 2
.#define bfd_mach_fr300 300
.#define bfd_mach_fr400 400
+.#define bfd_mach_fr450 450
.#define bfd_mach_frvtomcat 499 {* fr500 prototype *}
.#define bfd_mach_fr500 500
.#define bfd_mach_fr550 550
#define bfd_mach_frvsimple 2
#define bfd_mach_fr300 300
#define bfd_mach_fr400 400
+#define bfd_mach_fr450 450
#define bfd_mach_frvtomcat 499 /* fr500 prototype */
#define bfd_mach_fr500 500
#define bfd_mach_fr550 550
static const bfd_arch_info_type arch_info_400
= FRV_ARCH (bfd_mach_fr400, "fr400", FALSE, &arch_info_300);
+static const bfd_arch_info_type arch_info_450
+ = FRV_ARCH (bfd_mach_fr450, "fr450", FALSE, &arch_info_400);
+
static const bfd_arch_info_type arch_info_500
- = FRV_ARCH (bfd_mach_fr500, "fr500", FALSE, &arch_info_400);
+ = FRV_ARCH (bfd_mach_fr500, "fr500", FALSE, &arch_info_450);
static const bfd_arch_info_type arch_info_550
= FRV_ARCH (bfd_mach_fr550, "fr550", FALSE, &arch_info_500);
default: break;
case EF_FRV_CPU_FR550: return bfd_mach_fr550;
case EF_FRV_CPU_FR500: return bfd_mach_fr500;
+ case EF_FRV_CPU_FR450: return bfd_mach_fr450;
+ case EF_FRV_CPU_FR405: return bfd_mach_fr400;
case EF_FRV_CPU_FR400: return bfd_mach_fr400;
case EF_FRV_CPU_FR300: return bfd_mach_fr300;
case EF_FRV_CPU_SIMPLE: return bfd_mach_frvsimple;
return TRUE;
}
+/* Return true if the architecture described by elf header flag
+ EXTENSION is an extension of the architecture described by BASE. */
+
+static bfd_boolean
+frv_elf_arch_extension_p (flagword base, flagword extension)
+{
+ if (base == extension)
+ return TRUE;
+
+ /* CPU_GENERIC code can be merged with code for a specific
+ architecture, in which case the result is marked as being
+ for the specific architecture. Everything is therefore
+ an extension of CPU_GENERIC. */
+ if (base == EF_FRV_CPU_GENERIC)
+ return TRUE;
+
+ if (extension == EF_FRV_CPU_FR450)
+ if (base == EF_FRV_CPU_FR400 || base == EF_FRV_CPU_FR405)
+ return TRUE;
+
+ if (extension == EF_FRV_CPU_FR405)
+ if (base == EF_FRV_CPU_FR400)
+ return TRUE;
+
+ return FALSE;
+}
+
/* Merge backend specific data from an object file to the output
object file when linking. */
the generic cpu). */
new_partial = (new_flags & EF_FRV_CPU_MASK);
old_partial = (old_flags & EF_FRV_CPU_MASK);
- if (new_partial == old_partial)
- ;
-
- else if (new_partial == EF_FRV_CPU_GENERIC)
+ if (frv_elf_arch_extension_p (new_partial, old_partial))
;
- else if (old_partial == EF_FRV_CPU_GENERIC)
+ else if (frv_elf_arch_extension_p (old_partial, new_partial))
old_flags = (old_flags & ~EF_FRV_CPU_MASK) | new_partial;
else
case EF_FRV_CPU_SIMPLE: strcat (new_opt, " -mcpu=simple"); break;
case EF_FRV_CPU_FR550: strcat (new_opt, " -mcpu=fr550"); break;
case EF_FRV_CPU_FR500: strcat (new_opt, " -mcpu=fr500"); break;
+ case EF_FRV_CPU_FR450: strcat (new_opt, " -mcpu=fr450"); break;
+ case EF_FRV_CPU_FR405: strcat (new_opt, " -mcpu=fr405"); break;
case EF_FRV_CPU_FR400: strcat (new_opt, " -mcpu=fr400"); break;
case EF_FRV_CPU_FR300: strcat (new_opt, " -mcpu=fr300"); break;
case EF_FRV_CPU_TOMCAT: strcat (new_opt, " -mcpu=tomcat"); break;
case EF_FRV_CPU_SIMPLE: strcat (old_opt, " -mcpu=simple"); break;
case EF_FRV_CPU_FR550: strcat (old_opt, " -mcpu=fr550"); break;
case EF_FRV_CPU_FR500: strcat (old_opt, " -mcpu=fr500"); break;
+ case EF_FRV_CPU_FR450: strcat (old_opt, " -mcpu=fr450"); break;
+ case EF_FRV_CPU_FR405: strcat (old_opt, " -mcpu=fr405"); break;
case EF_FRV_CPU_FR400: strcat (old_opt, " -mcpu=fr400"); break;
case EF_FRV_CPU_FR300: strcat (old_opt, " -mcpu=fr300"); break;
case EF_FRV_CPU_TOMCAT: strcat (old_opt, " -mcpu=tomcat"); break;
case EF_FRV_CPU_SIMPLE: fprintf (file, " -mcpu=simple"); break;
case EF_FRV_CPU_FR550: fprintf (file, " -mcpu=fr550"); break;
case EF_FRV_CPU_FR500: fprintf (file, " -mcpu=fr500"); break;
+ case EF_FRV_CPU_FR450: fprintf (file, " -mcpu=fr450"); break;
+ case EF_FRV_CPU_FR405: fprintf (file, " -mcpu=fr405"); break;
case EF_FRV_CPU_FR400: fprintf (file, " -mcpu=fr400"); break;
case EF_FRV_CPU_FR300: fprintf (file, " -mcpu=fr300"); break;
case EF_FRV_CPU_TOMCAT: fprintf (file, " -mcpu=tomcat"); break;
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+ * frv.cpu (define-arch frv): Add fr450 mach.
+ (define-mach fr450): New.
+ (define-model fr450): New. Add profile units to every fr450 insn.
+ (define-attr UNIT): Add MDCUTSSI.
+ (define-attr FR450-MAJOR): New enum. Add to every fr450 insn.
+ (define-attr AUDIO): New boolean.
+ (f-LRAE, f-LRAD, f-LRAS, f-TLBPRopx, f-TLBPRL)
+ (f-LRA-null, f-TLBPR-null): New fields.
+ (scr0, scr1, scr2, scr3, imavr1, damvr1, cxnr, ttbr)
+ (tplr, tppr, tpxr, timerh, timerl, timerd, btbr): New SPRs.
+ (LRAE, LRAD, LRAS, TLBPRopx, TLBPRL): New operands.
+ (LRA-null, TLBPR-null): New macros.
+ (iacc-multiply-r-r, slass, scutss, int-arith-ss-r-r): Add AUDIO attr.
+ (load-real-address): New macro.
+ (lrai, lrad, tlbpr): New instructions.
+ (media-cut-acc, media-cut-acc-ss): Add fr450-major argument.
+ (mcut, mcuti, mcutss, mcutssi): Adjust accordingly.
+ (mdcutssi): Change UNIT attribute to MDCUTSSI.
+ (media-low-clear-semantics, media-scope-limit-semantics)
+ (media-quad-limit, media-quad-shift): New macros.
+ (mqlclrhs, mqlmths, mqsllhi, mqsrahi): New instructions.
+ * frv.opc (frv_is_branch_major, frv_is_float_major, frv_is_media_major)
+ (frv_is_branch_insn, frv_is_float_insn, frv_is_media_insn)
+ (frv_vliw_reset, frv_vliw_add_insn): Handle bfd_mach_fr450.
+ (fr450_unit_mapping): New array.
+ (fr400_unit_mapping, fr500_unit_mapping, fr550_unit_mapping): Add entry
+ for new MDCUTSSI unit.
+ (fr450_check_insn_major_constraints): New function.
+ (check_insn_major_constraints): Use it.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
* frv.cpu (nsdiv, nudiv, nsdivi, nudivi): Remove fr400 profiling unit.
(scutss): Change unit to I0.
(calll, callil, ccalll): Add missing FR550-MAJOR and profile unit.
(name frv) ; name of cpu architecture
(comment "Fujitsu FRV")
(insn-lsb0? #t)
- (machs frv fr550 fr500 fr400 tomcat simple)
+ (machs frv fr550 fr500 fr450 fr400 tomcat simple)
(isas frv)
)
)
)
\f
+; FR450 machine
+(define-mach
+ (name fr450)
+ (comment "FR450 cpu")
+ (cpu frvbf)
+)
+(define-model
+ (name fr450) (comment "FR450 model") (attrs)
+ (mach fr450)
+ (pipeline all "" () ((fetch) (decode) (execute) (writeback)))
+ ; `state' is a list of variables for recording model state
+ (state
+ ; State items
+ ; These are all masks with each bit representing one register.
+ (prev-fp-load DI) ; Previous use of FR register was floating point load
+ (prev-fr-p4 DI) ; Previous use of FR register was media unit 4
+ (prev-fr-p6 DI) ; Previous use of FR register was media unit 6
+ (prev-acc-p2 DI) ; Previous use of ACC register was media unit 2
+ (prev-acc-p4 DI) ; Previous use of ACC register was media unit 4
+ (cur-fp-load DI) ; Current use of FR register is floating point load
+ (cur-fr-p4 DI) ; Current use of FR register is media unit 4
+ (cur-fr-p6 DI) ; Current use of FR register is media unit 6
+ (cur-acc-p2 DI) ; Current use of ACC register is media unit 2
+ (cur-acc-p4 DI) ; Current use of ACC register is media unit 4
+ )
+ (unit u-exec "Execution Unit" ()
+ 1 1 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Basic integer insn unit
+ (unit u-integer "Integer Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Integer multiplication unit
+ (unit u-imul "Integer Multiplication Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ ((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Integer division unit
+ (unit u-idiv "Integer Division Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ ((GRk INT -1) (ICCi_1 INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Branch unit
+ (unit u-branch "Branch Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)
+ (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+ ((pc)) ; outputs
+ () ; profile action (default)
+ )
+ ; Trap unit
+ (unit u-trap "Trap Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)
+ (ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Condition code check unit
+ (unit u-check "Check Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; GR set half unit
+ (unit u-set-hilo "GR Set Half" ()
+ 1 1 ; issue done
+ () ; state
+ () ; inputs
+ ((GRkhi INT -1) (GRklo INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; GR load unit -- TODO doesn't handle quad
+ (unit u-gr-load "GR Load Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ ((GRk INT -1) (GRdoublek INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; GR store unit -- TODO doesn't handle quad
+ (unit u-gr-store "GR Store Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; FR load unit -- TODO doesn't handle quad
+ (unit u-fr-load "FR Load Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ ((FRintk INT -1) (FRdoublek INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; FR store unit -- TODO doesn't handle quad
+ (unit u-fr-store "FR Store Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Swap unit
+ (unit u-swap "Swap Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ ((GRk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; FR Move to GR unit
+ (unit u-fr2gr "FR Move to GR Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRintk INT -1)) ; inputs
+ ((GRj INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; SPR Move to GR unit
+ (unit u-spr2gr "SPR Move to GR Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((spr INT -1)) ; inputs
+ ((GRj INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; GR Move to FR unit
+ (unit u-gr2fr "GR Move to FR Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRj INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; GR Move to SPR unit
+ (unit u-gr2spr "GR Move to SPR Unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRj INT -1)) ; inputs
+ ((spr INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Media unit M1 -- see table 14-8 in the fr450 LSI
+ (unit u-media-1 "Media-1 unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1) (FRintj INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-1-quad "Media-1-quad unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1) (FRintj INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" ()
+ 1 1 ; issue done
+ () ; state
+ () ; inputs
+ ((FRkhi INT -1) (FRklo INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Media unit M2 -- see table 14-8 in the fr450 LSI
+ (unit u-media-2 "Media-2 unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1) (FRintj INT -1)) ; inputs
+ ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-2-quad "Media-2-quad unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1) (FRintj INT -1)) ; inputs
+ ((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-2-acc "Media-2-acc unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((ACC40Si INT -1)) ; inputs
+ ((ACC40Sk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-2-acc-dual "Media-2-acc-dual unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((ACC40Si INT -1)) ; inputs
+ ((ACC40Sk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-2-add-sub "Media-2-add-sub unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((ACC40Si INT -1)) ; inputs
+ ((ACC40Sk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((ACC40Si INT -1)) ; inputs
+ ((ACC40Sk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Media unit M3 -- see table 14-8 in the fr450 LSI
+ (unit u-media-3 "Media-3 unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1) (FRintj INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-3-dual "Media-3-dual unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-3-quad "Media-3-quad unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1) (FRintj INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Media unit M4 -- see table 14-8 in the fr450 LSI
+ (unit u-media-4 "Media-4 unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((ACC40Si INT -1) (FRintj INT -1)) ; inputs
+ ((ACC40Sk INT -1) (FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-4-accg "Media-4-accg unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((ACCGi INT -1) (FRinti INT -1)) ; inputs
+ ((ACCGk INT -1) (FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-4-acc-dual "Media-4-acc-dual unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((ACC40Si INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ (unit u-media-4-mclracca "Media-4 unit for MCLRACC with #A=1" ()
+ 1 1 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Media unit M6 -- see table 14-8 in the fr450 LSI
+ (unit u-media-6 "Media-6 unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Media unit M7 -- see table 14-8 in the fr450 LSI
+ (unit u-media-7 "Media-1 unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1) (FRintj INT -1)) ; inputs
+ ((FCCk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Media Dual Expand unit
+ (unit u-media-dual-expand "Media Dual Expand unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRinti INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Media Dual half to byte unit
+ (unit u-media-dual-htob "Media Half to byte" ()
+ 1 1 ; issue done
+ () ; state
+ ((FRintj INT -1)) ; inputs
+ ((FRintk INT -1)) ; outputs
+ () ; profile action (default)
+ )
+ ; Barrier unit
+ (unit u-barrier "Barrier unit" ()
+ 1 1 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Memory Barrier unit
+ (unit u-membar "Memory Barrier unit" ()
+ 1 1 ; issue done
+ () ; state
+ () ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Insn cache invalidate unit
+ (unit u-ici "Insn cache invalidate unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Data cache invalidate unit
+ (unit u-dci "Data cache invalidate unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Data cache flush unit
+ (unit u-dcf "Data cache flush unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Insn cache preload unit
+ (unit u-icpl "Insn cache preload unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Data cache preload unit
+ (unit u-dcpl "Data cache preload unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Insn cache unlock unit
+ (unit u-icul "Insn cache unlock unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+ ; Data cache unlock unit
+ (unit u-dcul "Data cache unlock unit" ()
+ 1 1 ; issue done
+ () ; state
+ ((GRi INT -1) (GRj INT -1)) ; inputs
+ () ; outputs
+ () ; profile action (default)
+ )
+)
+\f
; Simple machine - single issue integer machine
(define-mach
(name simple)
SCAN ; scan, scani slotted differently on different machines
DCPL ; dcpl slotted differently on different machines
MDUALACC ; media dual acc slotted differently on different machines
+ MDCUTSSI ; mdcutssi insn slotted differently on different machines
MCLRACC-1; mclracc A==1 slotted differently on different machines
NUM_UNITS
)
(define-attr
(for insn)
(type enum)
+ (name FR450-MAJOR)
+ (comment "fr450 major insn categories")
+ ; The order of declaration is significant. Keep variations on the same major
+ ; together.
+ (values NONE
+ I-1 I-2 I-3 I-4 I-5
+ B-1 B-2 B-3 B-4 B-5 B-6
+ C-1 C-2
+ M-1 M-2 M-3 M-4 M-5 M-6
+ )
+)
+(define-attr
+ (for insn)
+ (type enum)
(name FR500-MAJOR)
(comment "fr500 major insn categories")
; The order of declaration is significant. Keep variations on the same major
(name PRESERVE-OVF)
(comment "Preserve value of MSR.OVF")
)
+; "Audio" instruction provided by the fr405 but not the original fr400 core.
+(define-attr
+ (for insn)
+ (type boolean)
+ (name AUDIO)
+ (comment "Audio instruction added with FR405")
+)
; null attribute -- used as a place holder for where an attribue is required.
(define-attr
(for insn)
pc)))
)
+(dnf f-LRAE "Load Real Address E flag" () 5 1)
+(dnf f-LRAD "Load Real Address D flag" () 4 1)
+(dnf f-LRAS "Load Real Address S flag" () 3 1)
+
+(dnf f-TLBPRopx "TLB Probe operation number" () 28 3)
+(dnf f-TLBPRL "TLB Probe L flag" () 25 1)
+
(dnf f-ICCi_1-null "null field" (RESERVED) 11 2)
(dnf f-ICCi_2-null "null field" (RESERVED) 26 2)
(dnf f-ICCi_3-null "null field" (RESERVED) 1 2)
(dnf f-misc-null-10 "null field" (RESERVED) 16 5)
(dnf f-misc-null-11 "null field" (RESERVED) 5 1)
+(dnf f-LRA-null "null field" (RESERVED) 2 3)
+(dnf f-TLBPR-null "null field" (RESERVED) 30 2)
+
(dnf f-LI-off "null field" (RESERVED) 25 1)
(dnf f-LI-on "null field" (RESERVED) 25 1)
\f
(sr0 768) (sr1 769) (sr2 770) (sr3 771)
+ (scr0 832) (scr1 833) (scr2 834) (scr3 835)
+
(fsr0 1024) (fsr1 1025) (fsr2 1026) (fsr3 1027)
(fsr4 1028) (fsr5 1029) (fsr6 1030) (fsr7 1031)
(fsr8 1032) (fsr9 1033) (fsr10 1034) (fsr11 1035)
(dampr60 1916) (dampr61 1917) (dampr62 1918) (dampr63 1919)
(amcr 1920) (stbar 1921) (mmcr 1922)
- (dcr 2048) (brr 2049) (nmar 2050)
+ (iamvr1 1925) (damvr1 1927)
+ (cxnr 1936) (ttbr 1937) (tplr 1938) (tppr 1939)
+ (tpxr 1940)
+ (timerh 1952) (timerl 1953) (timerd 1954)
+ (dcr 2048) (brr 2049) (nmar 2050) (btbr 2051)
(ibar0 2052) (ibar1 2053) (ibar2 2054) (ibar3 2055)
(dbar0 2056) (dbar1 2057) (dbar2 2058) (dbar3 2059)
(define-hardware
(name h-iacc0)
(comment "64 bit signed accumulator")
- (attrs PROFILE VIRTUAL (MACH fr400))
+ (attrs PROFILE VIRTUAL (MACH fr400,fr450))
(type register DI (1))
(indices extern-keyword iacc0-names)
; The single 64-bit integer accumulator is made up of two 32 bit
(dnop label16 "18 bit pc relative address" () h-iaddr f-label16)
(dnop label24 "26 bit pc relative address" () h-iaddr f-label24)
+(dnop LRAE "Load Real Address E flag" () h-uint f-LRAE)
+(dnop LRAD "Load Real Address D flag" () h-uint f-LRAD)
+(dnop LRAS "Load Real Address S flag" () h-uint f-LRAS)
+
+(dnop TLBPRopx "TLB Probe operation number" () h-uint f-TLBPRopx)
+(dnop TLBPRL "TLB Probe L flag" () h-uint f-TLBPRL)
+
(define-operand
(name A0)
(comment "A==0 operand of mclracc")
(define-pmacro (misc-null-10) (f-misc-null-10 0))
(define-pmacro (misc-null-11) (f-misc-null-11 0))
+(define-pmacro (LRA-null) (f-LRA-null 0))
+(define-pmacro (TLBPR-null) (f-TLBPR-null 0))
+
(define-pmacro (LI-on) (f-LI-on 1))
(define-pmacro (LI-off) (f-LI-off 0))
\f
(define-pmacro (int-logic-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk")
(+ pack GRk op GRi (ICCi_1-null) ope GRj)
(set GRk (operation GRi GRj))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(dni not
("not")
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
("not$pack $GRj,$GRk")
(+ pack GRk OP_01 (rs-null) (ICCi_1-null) OPE2_06 GRj)
(set GRk (inv GRj))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
(dni sdiv
"signed division"
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1))
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"sdiv$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0E GRj)
(sequence ()
(c-call VOID "@cpu@_signed_integer_divide"
GRi GRj (index-of GRk) 0)
(clobber GRk))
- ((fr400 (unit u-idiv))
+ ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni udiv
"unsigned division reg/reg"
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1))
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"udiv$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0F GRj)
(sequence ()
(c-call VOID "@cpu@_unsigned_integer_divide"
GRi GRj (index-of GRk) 0)
(clobber GRk))
- ((fr400 (unit u-idiv))
+ ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(define-pmacro (multiply-r-r name signop op ope comment)
(dni name
(comment)
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1))
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRdoublek")
(+ pack GRdoublek op GRi (ICCi_1-null) ope GRj)
(set GRdoublek (mul DI (signop DI GRi) (signop DI GRj)))
- ((fr400 (unit u-imul))
+ ((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
)
(define-pmacro (iacc-multiply-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT IACC) (FR400-MAJOR I-1) (MACH fr400))
+ ((UNIT IACC) (MACH fr400,fr450)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
(.str name "$pack $GRi,$GRj")
(+ pack (rd-null) op GRi ope GRj)
((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj)))
- ((fr400 (unit u-integer)))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer)))
)
)
(define-pmacro (int-shift-r-r name op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk")
(+ pack GRk op GRi (ICCi_1-null) ope GRj)
(set GRk (name GRi (and GRj #x1f)))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(dni slass
"shift left arith reg/reg with saturation"
- ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400))
+ ((UNIT IALL) (MACH fr400,fr450)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
"slass$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_46 GRi OPE1_02 GRj)
(set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj))
(dni scutss
"Integer accumulator cut with saturation"
- ((UNIT I0) (FR400-MAJOR I-1) (MACH fr400))
+ ((UNIT I0) (MACH fr400,fr450)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
"scutss$pack $GRj,$GRk"
(+ pack GRk OP_46 (rs-null) OPE1_04 GRj)
(set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj))
(dni scan
"scan"
- ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"scan$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_0B GRi (ICCi_1-null) OPE2_00 GRj)
(scan-semantics GRi GRj GRk)
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
(define-pmacro (conditional-int-logic name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(set GRk (operation GRi GRj)))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(dni cnot
"conditional not"
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"cnot$pack $GRj,$GRk,$CCi,$cond"
(+ pack GRk OP_5A (rs-null) CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(set GRk (inv GRj)))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
(dni csmul
"conditional signed multiply"
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond"
(+ pack GRdoublek OP_58 GRi CCi cond OPE4_2 GRj)
(if (eq CCi (or cond 2))
(set GRdoublek (mul DI (ext DI GRi) (ext DI GRj))))
- ((fr400 (unit u-imul))
+ ((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
(dni csdiv
"conditional signed division"
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond"
(+ pack GRk OP_58 GRi CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(c-call VOID "@cpu@_signed_integer_divide"
GRi GRj (index-of GRk) 0)
(clobber GRk)))
- ((fr400 (unit u-idiv))
+ ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni cudiv
"conditional unsigned division"
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond"
(+ pack GRk OP_59 GRi CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(c-call VOID "@cpu@_unsigned_integer_divide"
GRi GRj (index-of GRk) 0)
(clobber GRk)))
- ((fr400 (unit u-idiv))
+ ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(define-pmacro (conditional-shift name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(set GRk (operation GRi (and GRj #x1f))))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(dni cscan
"conditional scan"
- ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"cscan$pack $GRi,$GRj,$GRk,$CCi,$cond"
(+ pack GRk OP_65 GRi CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(scan-semantics GRi GRj GRk))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
(define-pmacro (int-arith-cc-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(int-arith-cc-semantics operation ICCi_1)
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (int-logic-cc-r-r name op ope comment)
(dni (.sym name cc)
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(int-logic-cc-semantics name ICCi_1)
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (int-shift-cc-r-r name l-r op ope comment)
(dni (.sym name cc)
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(int-shift-cc-semantics name l-r ICCi_1)
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (multiply-cc-r-r name signop op ope comment)
(dni name
(comment)
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1))
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRdoublek,$ICCi_1")
(+ pack GRdoublek op GRi ICCi_1 ope GRj)
(multiply-cc-semantics signop GRi GRj GRdoublek ICCi_1)
- ((fr400 (unit u-imul))
+ ((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
)
(define-pmacro (conditional-int-arith-cc name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(int-arith-cc-semantics operation
(reg h-iccr (and (index-of CCi) 3))))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(dni csmulcc
"conditional signed multiply and set condition code"
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond"
(+ pack GRdoublek OP_59 GRi CCi cond OPE4_2 GRj)
(if (eq CCi (or cond 2))
(multiply-cc-semantics ext GRi GRj GRdoublek
(reg h-iccr (and (index-of CCi) 3))))
- ((fr400 (unit u-imul))
+ ((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
(define-pmacro (conditional-int-logic-cc name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(int-logic-cc-semantics operation
(reg h-iccr (and (index-of CCi) 3))))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (conditional-int-shift-cc name l-r op ope comment)
(dni (.sym c name cc)
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str (.sym c name cc) "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(int-shift-cc-semantics name l-r
(reg h-iccr (and (index-of CCi) 3))))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (int-arith-x-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(set GRk ((.sym operation c) GRi GRj (cbit ICCi_1)))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (int-arith-x-cc-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(sequence ((WI tmp) (QI cc))
(set-z-and-n cc tmp)
(set GRk tmp)
(set ICCi_1 cc))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (int-arith-ss-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT IALL) (FR400-MAJOR I-1) (MACH fr400))
+ ((UNIT IALL) (MACH fr400,fr450)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
(.str name "$pack $GRi,$GRj,$GRk")
(+ pack GRk op GRi ope GRj)
(sequence ()
((lt GRi 0) (const #x80000000))
(else (const 0)))))
)
- ((fr400 (unit u-integer)))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer)))
)
)
(define-pmacro (int-logic-r-simm name operation op comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s12,$GRk")
(+ pack GRk op GRi s12)
(set GRk (operation GRi s12))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(dni sdivi
"signed division reg/immed"
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1))
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"sdivi$pack $GRi,$s12,$GRk"
(+ pack GRk OP_1E GRi s12)
(sequence ()
(c-call VOID "@cpu@_signed_integer_divide"
GRi s12 (index-of GRk) 0)
(clobber GRk))
- ((fr400 (unit u-idiv))
+ ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni udivi
"unsigned division reg/immed"
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1))
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"udivi$pack $GRi,$s12,$GRk"
(+ pack GRk OP_1F GRi s12)
(sequence ()
(c-call VOID "@cpu@_unsigned_integer_divide"
GRi s12 (index-of GRk) 0)
(clobber GRk))
- ((fr400 (unit u-idiv))
+ ((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(define-pmacro (multiply-r-simm name signop op comment)
(dni name
(comment)
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1))
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s12,$GRdoublek")
(+ pack GRdoublek op GRi s12)
(set GRdoublek (mul DI (signop DI GRi) (signop DI s12)))
- ((fr400 (unit u-imul))
+ ((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
)
(define-pmacro (int-shift-r-simm name op comment)
(dni (.sym name i)
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name i) "$pack $GRi,$s12,$GRk")
(+ pack GRk op GRi s12)
(set GRk (name GRi (and s12 #x1f)))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(dni scani
"scan immediate"
- ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"scani$pack $GRi,$s12,$GRk"
(+ pack GRk OP_47 GRi s12)
(scan-semantics GRi s12 GRk)
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
(define-pmacro (int-arith-cc-r-simm name operation op comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(sequence ((BI tmp) (QI cc) (SI result))
(set-z-and-n cc result)
(set GRk result)
(set ICCi_1 cc))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (int-logic-cc-r-simm name op comment)
(dni (.sym name icc)
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(sequence ((SI tmp))
(set tmp (name GRi s10))
(set GRk tmp)
(set-z-and-n ICCi_1 tmp))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (multiply-cc-r-simm name signop op comment)
(dni name
(comment)
- ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) (FR400-MAJOR I-1))
+ ((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s10,$GRdoublek,$ICCi_1")
(+ pack GRdoublek op GRi ICCi_1 s10)
(multiply-cc-semantics signop GRi s10 GRdoublek ICCi_1)
- ((fr400 (unit u-imul))
+ ((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
)
(define-pmacro (int-shift-cc-r-simm name l-r op comment)
(dni (.sym name icc)
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(sequence ((WI shift) (SI tmp) (QI cc))
(set GRk tmp)
(set-z-and-n cc tmp)
(set ICCi_1 cc))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (int-arith-x-r-simm name operation op comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(set GRk ((.sym operation c) GRi s10 (cbit ICCi_1)))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(define-pmacro (int-arith-x-cc-r-simm name operation op comment)
(dni name
(comment)
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(sequence ((WI tmp) (QI cc))
(set-z-and-n cc tmp)
(set GRk tmp)
(set ICCi_1 cc))
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(dni cmpb
"Compare bytes"
- ((UNIT IALL) (FR400-MAJOR I-1) (FR550-MAJOR I-1) (MACH fr400,fr550))
+ ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"cmpb$pack $GRi,$GRj,$ICCi_1"
(+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0C GRj)
(sequence ((QI cc))
(set-v cc (eq (and GRi #x0000ff00) (and GRj #x0000ff00)))
(set-c cc (eq (and GRi #x000000ff) (and GRj #x000000ff)))
(set ICCi_1 cc))
- ((fr400 (unit u-integer)) (fr550 (unit u-integer)))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+ (fr550 (unit u-integer)))
)
(dni cmpba
"OR of Compare bytes"
- ((UNIT IALL) (FR400-MAJOR I-1) (FR550-MAJOR I-1) (MACH fr400,fr550))
+ ((UNIT IALL) (MACH fr400,fr450,fr550) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"cmpba$pack $GRi,$GRj,$ICCi_1"
(+ pack (GRk-null) OP_00 GRi ICCi_1 OPE2_0D GRj)
(sequence ((QI cc))
(eq (and GRi #x000000ff)
(and GRj #x000000ff))))))
(set ICCi_1 cc))
- ((fr400 (unit u-integer)) (fr550 (unit u-integer)))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
+ (fr550 (unit u-integer)))
)
; Format: Load immediate
;
(dni setlo
"set low order bits"
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"setlo$pack $ulo16,$GRklo"
(+ pack GRk OP_3D (misc-null-4) u16)
(set GRklo u16)
- ((fr400 (unit u-set-hilo))
+ ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo))
(fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo)))
)
(dni sethi
"set high order bits"
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"sethi$pack $uhi16,$GRkhi"
(+ pack GRkhi OP_3E (misc-null-4) u16)
(set GRkhi u16)
- ((fr400 (unit u-set-hilo))
+ ((fr400 (unit u-set-hilo)) (fr450 (unit u-set-hilo))
(fr500 (unit u-set-hilo)) (fr550 (unit u-set-hilo)))
)
(dni setlos
"set low order bits and extend sign"
- ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"setlos$pack $slo16,$GRk"
(+ pack GRk OP_3F (misc-null-4) s16)
(set GRk s16)
- ((fr400 (unit u-integer))
+ ((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
(define-pmacro (load-gr-r name mode op ope comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2))
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2))
(.str name "$pack @($GRi,$GRj),$GRk")
(+ pack GRk op GRi ope GRj)
(set GRk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))
- ((fr400 (unit u-gr-load))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
(fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
)
)
(define-pmacro (load-fr-r name mode op ope comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) FR-ACCESS)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS)
(.str name "$pack @($GRi,$GRj),$FRintk")
(+ pack FRintk op GRi ope GRj)
(set FRintk (c-call mode (.str "@cpu@_read_mem_" mode) pc (add GRi GRj)))
- ((fr400 (unit u-fr-load))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
(fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
)
)
name not_gr mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr)
(.str name "$pack @($GRi,$GRj),$" regtype "doublek")
(+ pack (.sym regtype doublek) op GRi ope GRj)
(sequence ((WI address))
)
(load-double-r-r ldd 0 DI OP_02 OPE1_05 GR NA
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load double word")
(load-double-r-r lddf 1 DF OP_02 OPE1_0B FR FR-ACCESS
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load double float")
(load-double-r-r lddc 1 DI OP_02 OPE1_0E CPR (MACH frv) ()
"Load coprocessor double")
(define-pmacro (load-gr-u name mode op ope comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2))
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2))
(.str name "$pack @($GRi,$GRj),$GRk")
(+ pack GRk op GRi ope GRj)
(load-gr-u-semantics mode)
- ((fr400 (unit u-gr-load))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
(fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
)
)
(define-pmacro (load-fr-u name mode op ope comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) FR-ACCESS)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) FR-ACCESS)
(.str name "$pack @($GRi,$GRj),$FRintk")
(+ pack FRintk op GRi ope GRj)
(load-non-gr-u-semantics mode FRint)
- ((fr400 (unit u-fr-load))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
(fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
)
)
(define-pmacro (load-double-gr-u name op ope comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2))
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2))
(.str name "$pack @($GRi,$GRj),$GRdoublek")
(+ pack GRdoublek op GRi ope GRj)
(load-double-gr-u-semantics)
- ((fr400 (unit u-gr-load))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
(fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
)
)
name mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr)
(.str name "$pack @($GRi,$GRj),$" regtype "doublek")
(+ pack (.sym regtype doublek) op GRi ope GRj)
(load-double-non-gr-u-semantics mode regtype)
)
(load-double-non-gr-u lddfu DF OP_02 OPE1_1B FR FR-ACCESS
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load double float, update index")
(load-double-non-gr-u lddcu DI OP_02 OPE1_1E CPR (MACH frv)
() "Load coprocessor double float, update index")
(define-pmacro (load-r-simm name mode op regtype attr profile comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr)
(.str name "$pack @($GRi,$d12),$" regtype "k")
(+ pack (.sym regtype k) op GRi d12)
(set (.sym regtype k)
)
(load-r-simm ldsbi QI OP_30 GR NA
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load signed byte")
(load-r-simm ldshi HI OP_31 GR NA
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load signed half")
(load-r-simm ldi SI OP_32 GR NA
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load word")
(load-r-simm ldubi UQI OP_35 GR NA
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load unsigned byte")
(load-r-simm lduhi UHI OP_36 GR NA
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load unsigned half")
(load-r-simm ldbfi UQI OP_38 FRint FR-ACCESS
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load byte float")
(load-r-simm ldhfi UHI OP_39 FRint FR-ACCESS
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load half float")
(load-r-simm ldfi SI OP_3A FRint FR-ACCESS
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load word float")
(define-pmacro (ne-load-r-simm
name not_gr mode op regtype attr profile comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) attr)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) attr)
(.str name "$pack @($GRi,$d12),$" regtype "doublek")
(+ pack (.sym regtype doublek) op GRi d12)
(sequence ((WI address))
)
(load-double-r-simm lddi 0 DI OP_33 GR NA
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load double word")
(load-double-r-simm lddfi 1 DF OP_3B FR FR-ACCESS
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load double float")
(define-pmacro (ne-load-double-r-simm
(define-pmacro (store-r-r name mode op ope reg attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
(.str name "$pack $" reg "k,@($GRi,$GRj)")
(+ pack (.sym reg k) op GRi ope GRj)
(c-call VOID (.str "@cpu@_write_mem_" mode)
)
(store-r-r stb QI OP_03 OPE1_00 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned byte")
(store-r-r sth HI OP_03 OPE1_01 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned half")
(store-r-r st SI OP_03 OPE1_02 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store word")
(store-r-r stbf QI OP_03 OPE1_08 FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store byte float")
(store-r-r sthf HI OP_03 OPE1_09 FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store half float")
(store-r-r stf SI OP_03 OPE1_0A FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store word float")
(store-r-r stc SI OP_03 OPE1_25 CPR (MACH frv) () "Store coprocessor word")
(define-pmacro (store-double-r-r name mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
(.str name "$pack $" regtype "doublek,@($GRi,$GRj)")
(+ pack (.sym regtype doublek) op GRi ope GRj)
(sequence ((WI address))
)
(store-double-r-r std DI OP_03 OPE1_03 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store double word")
(store-double-r-r stdf DF OP_03 OPE1_0B FR FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store double float")
(store-double-r-r stdc DI OP_03 OPE1_26 CPR (MACH frv)
(define-pmacro (store-r-r-u name mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
(.str name "$pack $" regtype "k,@($GRi,$GRj)")
(+ pack (.sym regtype k) op GRi ope GRj)
(sequence ((UWI address))
)
(store-r-r-u stbu QI OP_03 OPE1_10 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned byte, update index")
(store-r-r-u sthu HI OP_03 OPE1_11 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned half, update index")
(store-r-r-u stu WI OP_03 OPE1_12 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store word, update index")
(store-r-r-u stbfu QI OP_03 OPE1_18 FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store byte float, update index")
(store-r-r-u sthfu HI OP_03 OPE1_19 FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store half float, update index")
(store-r-r-u stfu SI OP_03 OPE1_1A FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store word float, update index")
(store-r-r-u stcu SI OP_03 OPE1_2D CPR (MACH frv) ()
name mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
(.str name "$pack $" regtype "doublek,@($GRi,$GRj)")
(+ pack (.sym regtype doublek) op GRi ope GRj)
(sequence ((WI address))
)
(store-double-r-r-u stdu DI OP_03 OPE1_13 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store double word, update index")
(store-double-r-r-u stdfu DF OP_03 OPE1_1B FR FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store double float,update index")
(store-double-r-r-u stdcu DI OP_03 OPE1_2E CPR (MACH frv) ()
"Store coprocessor double word, update index")
(define-pmacro (conditional-load name mode op ope regtype profile comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL)
(.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond")
(+ pack (.sym regtype k) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
)
(conditional-load cldsb QI OP_5E OPE4_0 GR
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load signed byte")
(conditional-load cldub UQI OP_5E OPE4_1 GR
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load unsigned byte")
(conditional-load cldsh HI OP_5E OPE4_2 GR
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load signed half")
(conditional-load clduh UHI OP_5E OPE4_3 GR
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load unsigned half")
(conditional-load cld SI OP_5F OPE4_0 GR
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load word")
(conditional-load cldbf UQI OP_60 OPE4_0 FRint
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load byte float")
(conditional-load cldhf UHI OP_60 OPE4_1 FRint
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load half float")
(conditional-load cldf SI OP_60 OPE4_2 FRint
- ((fr400 (unit u-fr-load)) (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
+ (fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
"Load word float")
(define-pmacro (conditional-load-double
name not_gr mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL attr)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL attr)
(.str name "$pack @($GRi,$GRj),$" regtype "doublek,$CCi,$cond")
(+ pack (.sym regtype doublek) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
)
(conditional-load-double cldd 0 DI OP_5F OPE4_1 GR NA
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
"Load double word")
(conditional-load-double clddf 1 DF OP_60 OPE4_3 FR FR-ACCESS
- ((fr400 (unit u-gr-load)) (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load)))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
+ (fr500 (unit u-gr-load)) (fr550 (unit u-fr-load)))
"Load double float")
(dni cldq
(define-pmacro (conditional-load-gr-u name mode op ope comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL)
(.str name "$pack @($GRi,$GRj),$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
pc address))
(if (ne (index-of GRi) (index-of GRk))
(set GRi address))))
- ((fr400 (unit u-gr-load))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
(fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
)
)
(define-pmacro (conditional-load-non-gr-u name mode op ope regtype comment)
(dni name
(comment)
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL FR-ACCESS)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS)
(.str name "$pack @($GRi,$GRj),$" regtype "k,$CCi,$cond")
(+ pack (.sym regtype k) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(c-call mode (.str "@cpu@_read_mem_" mode)
pc address))
(set GRi address)))
- ((fr400 (unit u-fr-load))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
(fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
)
)
(dni clddu
"Load double word, update"
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL)
"clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond"
(+ pack GRdoublek OP_62 GRi CCi cond OPE4_1 GRj)
(if (eq CCi (or cond 2))
(load-double-semantics 0 DI GR address GRj)
(if (ne (index-of GRi) (index-of GRdoublek))
(set GRi address))))
- ((fr400 (unit u-gr-load))
+ ((fr400 (unit u-gr-load)) (fr450 (unit u-gr-load))
(fr500 (unit u-gr-load)) (fr550 (unit u-gr-load)))
)
(dni clddfu
"Load double float, update"
- ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2) (FR400-MAJOR I-2) CONDITIONAL FR-ACCESS)
+ ((UNIT LOAD) (FR550-MAJOR I-3) (FR500-MAJOR I-2)
+ (FR400-MAJOR I-2) (FR450-MAJOR I-2) CONDITIONAL FR-ACCESS)
"clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond"
(+ pack FRdoublek OP_63 GRi CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(sequence ((WI address))
(load-double-semantics 1 DF FR address GRj)
(set GRi address)))
- ((fr400 (unit u-fr-load))
+ ((fr400 (unit u-fr-load)) (fr450 (unit u-fr-load))
(fr500 (unit u-fr-load)) (fr550 (unit u-fr-load)))
)
(define-pmacro (conditional-store name mode op ope regtype profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL)
(.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond")
(+ pack (.sym regtype k) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
)
(conditional-store cstb QI OP_64 OPE4_0 GR
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned byte")
(conditional-store csth HI OP_64 OPE4_1 GR
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned half")
(conditional-store cst SI OP_64 OPE4_2 GR
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store word")
(conditional-store cstbf QI OP_66 OPE4_0 FRint
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store byte float")
(conditional-store csthf HI OP_66 OPE4_1 FRint
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store half float")
(conditional-store cstf SI OP_66 OPE4_2 FRint
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store word float")
(define-pmacro (conditional-store-double
name mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr)
(.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond")
(+ pack (.sym regtype doublek) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
)
(conditional-store-double cstd DI OP_64 OPE4_3 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store double word")
(conditional-store-double cstdf DF OP_66 OPE4_3 FR FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store double float")
(dni cstq
name mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr)
(.str name "$pack $" regtype "k,@($GRi,$GRj),$CCi,$cond")
(+ pack (.sym regtype k) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
)
(conditional-store-u cstbu QI OP_67 OPE4_0 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned byte, update index")
(conditional-store-u csthu HI OP_67 OPE4_1 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned half, update index")
(conditional-store-u cstu SI OP_67 OPE4_2 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store word, update index")
(conditional-store-u cstbfu QI OP_68 OPE4_0 FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store byte float, update index")
(conditional-store-u csthfu HI OP_68 OPE4_1 FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store half float, update index")
(conditional-store-u cstfu SI OP_68 OPE4_2 FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store word float, update index")
(define-pmacro (conditional-store-double-u
name mode op ope regtype attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) CONDITIONAL attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) CONDITIONAL attr)
(.str name "$pack $" regtype "doublek,@($GRi,$GRj),$CCi,$cond")
(+ pack (.sym regtype doublek) op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
)
(conditional-store-double-u cstdu DI OP_67 OPE4_3 GR NA
- ((fr400 (unit u-gr-store))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
(fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store double word, update index")
(conditional-store-double-u cstdfu DF OP_68 OPE4_3 FR FR-ACCESS
- ((fr400 (unit u-fr-store))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
(fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store double float, update index")
(define-pmacro (store-r-simm name mode op regtype attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
(.str name "$pack $" regtype "k,@($GRi,$d12)")
(+ pack (.sym regtype k) op GRi d12)
(c-call VOID (.str "@cpu@_write_mem_" mode)
)
(store-r-simm stbi QI OP_50 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned byte")
(store-r-simm sthi HI OP_51 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store unsigned half")
(store-r-simm sti SI OP_52 GR NA
- ((fr400 (unit u-gr-store)) (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
+ (fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store word")
(store-r-simm stbfi QI OP_4E FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store byte float")
(store-r-simm sthfi HI OP_4F FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store half float")
(store-r-simm stfi SI OP_55 FRint FR-ACCESS
- ((fr400 (unit u-fr-store)) (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
+ (fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store word float")
(define-pmacro (store-double-r-simm name mode op regtype attr profile comment)
(dni name
(comment)
- ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3) (FR400-MAJOR I-3) attr)
+ ((UNIT STORE) (FR550-MAJOR I-4) (FR500-MAJOR I-3)
+ (FR400-MAJOR I-3) (FR450-MAJOR I-3) attr)
(.str name "$pack $" regtype "doublek,@($GRi,$d12)")
(+ pack (.sym regtype doublek) op GRi d12)
(sequence ((WI address))
)
(store-double-r-simm stdi DI OP_53 GR NA
- ((fr400 (unit u-gr-store))
+ ((fr400 (unit u-gr-store)) (fr450 (unit u-gr-store))
(fr500 (unit u-gr-store)) (fr550 (unit u-gr-store)))
"Store double word")
(store-double-r-simm stdfi DF OP_56 FR FR-ACCESS
- ((fr400 (unit u-fr-store))
+ ((fr400 (unit u-fr-store)) (fr450 (unit u-fr-store))
(fr500 (unit u-fr-store)) (fr550 (unit u-fr-store)))
"Store double float")
(dni swap
"Swap contents of memory with GR"
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2))
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
"swap$pack @($GRi,$GRj),$GRk"
(+ pack GRk OP_03 GRi OPE1_05 GRj)
(swap-semantics GRi GRj GRk)
- ((fr400 (unit u-swap))
+ ((fr400 (unit u-swap)) (fr450 (unit u-swap))
(fr500 (unit u-swap)) (fr550 (unit u-swap)))
)
(dni "swapi"
"Swap contents of memory with GR"
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2))
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
("swapi$pack @($GRi,$d12),$GRk")
(+ pack GRk OP_4D GRi d12)
(swap-semantics GRi d12 GRk)
- ((fr400 (unit u-swap))
+ ((fr400 (unit u-swap)) (fr450 (unit u-swap))
(fr500 (unit u-swap)) (fr550 (unit u-swap)))
)
(dni cswap
"Conditionally swap contents of memory with GR"
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2) CONDITIONAL)
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2) CONDITIONAL)
"cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond"
(+ pack GRk OP_65 GRi CCi cond OPE4_2 GRj)
(if (eq CCi (or cond 2))
(swap-semantics GRi GRj GRk))
- ((fr400 (unit u-swap))
+ ((fr400 (unit u-swap)) (fr450 (unit u-swap))
(fr500 (unit u-swap)) (fr550 (unit u-swap)))
)
(register-transfer movgf OP_03 OPE1_15
GRj FRintk I0
- ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS)
- ((fr400 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
+ ((FR500-MAJOR I-4) (FR550-MAJOR I-5)
+ (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS)
+ ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr))
+ (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
"transfer gr to fr")
(register-transfer movfg OP_03 OPE1_0D
FRintk GRj I0
- ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS)
- ((fr400 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
+ ((FR500-MAJOR I-4) (FR550-MAJOR I-5)
+ (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS)
+ ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr))
+ (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
"transfer fr to gr")
(define-pmacro (nextreg hw r offset) (reg hw (add (index-of r) offset)))
(dni movgfd
"move GR for FR double"
- ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS)
+ ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5)
+ (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS)
"movgfd$pack $GRj,$FRintk"
(+ pack FRintk OP_03 (rs-null) OPE1_16 GRj)
(register-transfer-double-from-gr-semantics 1)
; TODO -- doesn't handle second register in the pair
- ((fr400 (unit u-gr2fr))
+ ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr))
(fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
)
(dni movfgd
"move FR for GR double"
- ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) FR-ACCESS)
+ ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5)
+ (FR400-MAJOR I-4) (FR450-MAJOR I-4) FR-ACCESS)
"movfgd$pack $FRintk,$GRj"
(+ pack FRintk OP_03 (rs-null) OPE1_0E GRj)
(register-transfer-double-to-gr-semantics 1)
; TODO -- doesn't handle second register in the pair
- ((fr400 (unit u-fr2gr))
+ ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr))
(fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
)
)
(conditional-register-transfer cmovgf OP_69 OPE4_0 GRj FRintk I0
- ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4))
- ((fr400 (unit u-gr2fr)) (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
+ ((FR500-MAJOR I-4) (FR550-MAJOR I-5)
+ (FR400-MAJOR I-4) (FR450-MAJOR I-4))
+ ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr))
+ (fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
"transfer gr to fr")
(conditional-register-transfer cmovfg OP_69 OPE4_2 FRintk GRj I0
- ((FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4))
- ((fr400 (unit u-fr2gr)) (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
+ ((FR500-MAJOR I-4) (FR550-MAJOR I-5)
+ (FR400-MAJOR I-4) (FR450-MAJOR I-4))
+ ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr))
+ (fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
"transfer fr to gr")
(dni cmovgfd
"Conditional move GR to FR double"
- ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) CONDITIONAL FR-ACCESS)
+ ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5)
+ (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS)
"cmovgfd$pack $GRj,$FRintk,$CCi,$cond"
(+ pack FRintk OP_69 (rs-null) CCi cond OPE4_1 GRj)
(register-transfer-double-from-gr-semantics (eq CCi (or cond 2)))
; TODO -- doesn't handle extra registers in double
- ((fr400 (unit u-gr2fr))
+ ((fr400 (unit u-gr2fr)) (fr450 (unit u-gr2fr))
(fr500 (unit u-gr2fr)) (fr550 (unit u-gr2fr)))
)
(dni cmovfgd
"Conditional move FR to GR double"
- ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5) (FR400-MAJOR I-4) CONDITIONAL FR-ACCESS)
+ ((UNIT I0) (FR500-MAJOR I-4) (FR550-MAJOR I-5)
+ (FR400-MAJOR I-4) (FR450-MAJOR I-4) CONDITIONAL FR-ACCESS)
"cmovfgd$pack $FRintk,$GRj,$CCi,$cond"
(+ pack FRintk OP_69 (rs-null) CCi cond OPE4_3 GRj)
(register-transfer-double-to-gr-semantics (eq CCi (or cond 2)))
; TODO -- doesn't handle second register in the pair
- ((fr400 (unit u-fr2gr))
+ ((fr400 (unit u-fr2gr)) (fr450 (unit u-fr2gr))
(fr500 (unit u-fr2gr)) (fr550 (unit u-fr2gr)))
)
name op ope reg_src reg_targ unitname comment)
(dni name
(comment)
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2))
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
(.str name "$pack $" reg_src ",$" reg_targ)
(+ pack reg_targ op ope reg_src)
(set reg_targ reg_src)
- ((fr400 (unit unitname))
+ ((fr400 (unit unitname)) (fr450 (unit unitname))
(fr500 (unit unitname)) (fr550 (unit unitname)))
)
)
(define-pmacro (conditional-branch-i prefix cc op cond comment)
(dni (.sym prefix cc)
(comment)
- ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1))
+ ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+ (FR400-MAJOR B-1) (FR450-MAJOR B-1))
(.str (.sym prefix cc) "$pack $ICCi_2,$hint,$label16")
(+ pack (.sym ICC_ cc) ICCi_2 op hint label16)
(sequence ()
(c-call VOID "@cpu@_model_branch" label16 hint)
(if (cond ICCi_2)
(set pc label16)))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
)
(dni bra
"integer branch equal"
- ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1))
+ ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+ (FR400-MAJOR B-1) (FR450-MAJOR B-1))
"bra$pack $hint_taken$label16"
(+ pack ICC_ra (ICCi_2-null) OP_06 hint_taken label16)
(sequence ()
(c-call VOID "@cpu@_model_branch" label16 hint_taken)
(set pc label16))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni bno
"integer branch never"
- ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1))
+ ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+ (FR400-MAJOR B-1) (FR450-MAJOR B-1))
"bno$pack$hint_not_taken"
(+ pack ICC_nev (ICCi_2-null) OP_06 hint_not_taken (label16-null))
(c-call VOID "@cpu@_model_branch" label16 hint_not_taken)
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(define-pmacro (conditional-branch-f prefix cc op cond comment)
(dni (.sym prefix cc)
(comment)
- ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+ (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS)
(.str (.sym prefix cc) "$pack $FCCi_2,$hint,$label16")
(+ pack (.sym FCC_ cc) FCCi_2 op hint label16)
(sequence ()
(c-call VOID "@cpu@_model_branch" label16 hint)
(if (cond FCCi_2) (set pc label16)))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
)
(dni fbra
"float branch equal"
- ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+ (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS)
"fbra$pack $hint_taken$label16"
(+ pack FCC_ra (FCCi_2-null) OP_07 hint_taken label16)
(sequence ()
(c-call VOID "@cpu@_model_branch" label16 hint_taken)
(set pc label16))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni fbno
"float branch never"
- ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1) (FR400-MAJOR B-1) FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-1) (FR550-MAJOR B-1)
+ (FR400-MAJOR B-1) (FR450-MAJOR B-1) FR-ACCESS)
"fbno$pack$hint_not_taken"
(+ pack FCC_nev (FCCi_2-null) OP_07 hint_not_taken (label16-null))
(c-call VOID "@cpu@_model_branch" label16 hint_not_taken)
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni bctrlr
"LCR conditional branch to lr"
- ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2))
+ ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+ (FR400-MAJOR B-2) (FR450-MAJOR B-2))
("bctrlr$pack $ccond,$hint")
(+ pack (cond-null) (ICCi_2-null) OP_0E hint OPE3_01 ccond (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint)
(ctrlr-branch-semantics (const BI 1) ccond))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(define-pmacro (conditional-branch-cclr prefix cc i-f op ope cond attr comment)
(dni (.sym prefix cc lr)
(comment)
- ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) attr)
+ ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+ (FR400-MAJOR B-3) (FR450-MAJOR B-3) attr)
(.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$hint")
(+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope
(ccond-null) (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint)
(if (cond (.sym i-f CCi_2)) (set pc (spr-lr))))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
)
(dni bralr
"integer cclr branch always"
- ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3))
+ ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+ (FR400-MAJOR B-3) (FR450-MAJOR B-3))
"bralr$pack$hint_taken"
(+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_02 (ccond-null) (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken)
(set pc (spr-lr)))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni bnolr
"integer cclr branch never"
- ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3))
+ ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+ (FR400-MAJOR B-3) (FR450-MAJOR B-3))
"bnolr$pack$hint_not_taken"
(+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_02 (ccond-null) (s12-null))
(c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken)
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni fbralr
"float cclr branch always"
- ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+ (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS)
"fbralr$pack$hint_taken"
(+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_06 (ccond-null) (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken)
(set pc (spr-lr)))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni fbnolr
"float cclr branch never"
- ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3) (FR400-MAJOR B-3) FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-3) (FR550-MAJOR B-3)
+ (FR400-MAJOR B-3) (FR450-MAJOR B-3) FR-ACCESS)
"fbnolr$pack$hint_not_taken"
(+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_06 (ccond-null) (s12-null))
(c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken)
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(define-pmacro (conditional-branch-ctrlr prefix cc i-f op ope cond attr comment)
(dni (.sym prefix cc lr)
(comment)
- ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) attr)
+ ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+ (FR400-MAJOR B-2) (FR450-MAJOR B-2) attr)
(.str (.sym prefix cc lr) "$pack $" i-f "CCi_2,$ccond,$hint")
(+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op hint ope ccond (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint)
(ctrlr-branch-semantics (cond (.sym i-f CCi_2)) ccond))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
)
(dni bcralr
"integer ctrlr branch always"
- ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2))
+ ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+ (FR400-MAJOR B-2) (FR450-MAJOR B-2))
"bcralr$pack $ccond$hint_taken"
(+ pack ICC_ra (ICCi_2-null) OP_0E hint_taken OPE3_03 ccond (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken)
(ctrlr-branch-semantics (const BI 1) ccond))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni bcnolr
"integer ctrlr branch never"
- ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2))
+ ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+ (FR400-MAJOR B-2) (FR450-MAJOR B-2))
"bcnolr$pack$hint_not_taken"
(+ pack ICC_nev (ICCi_2-null) OP_0E hint_not_taken OPE3_03 (ccond-null) (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken)
(ctrlr-branch-semantics (const BI 0) ccond))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni fcbralr
"float ctrlr branch always"
- ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) FR-ACCESS)
+ ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+ (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS)
"fcbralr$pack $ccond$hint_taken"
(+ pack FCC_ra (FCCi_2-null) OP_0E hint_taken OPE3_07 ccond (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint_taken)
(ctrlr-branch-semantics (const BI 1) ccond))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni fcbnolr
"float ctrlr branch never"
- ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2) (FR400-MAJOR B-2) FR-ACCESS)
+ ((UNIT B0) (FR500-MAJOR B-2) (FR550-MAJOR B-2)
+ (FR400-MAJOR B-2) (FR450-MAJOR B-2) FR-ACCESS)
"fcbnolr$pack$hint_not_taken"
(+ pack FCC_nev (FCCi_2-null) OP_0E hint_not_taken OPE3_07 (ccond-null) (s12-null))
(sequence ()
(c-call VOID "@cpu@_model_branch" (spr-lr) hint_not_taken)
(ctrlr-branch-semantics (const BI 0) ccond))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni jmpl
"jump and link"
- ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5))
+ ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+ (FR400-MAJOR I-5) (FR450-MAJOR I-5))
"jmpl$pack @($GRi,$GRj)"
(+ pack (misc-null-1) (LI-off) OP_0C GRi (misc-null-2) GRj)
(jump-and-link-semantics GRi GRj LI)
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni calll
"call and link"
- ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5))
+ ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+ (FR400-MAJOR I-5) (FR450-MAJOR I-5))
"calll$pack @($GRi,$GRj)"
(+ pack (misc-null-1) (LI-on) OP_0C GRi (misc-null-2) GRj)
(jump-and-link-semantics GRi GRj LI)
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni jmpil
"jump immediate and link"
- ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5))
+ ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+ (FR400-MAJOR I-5) (FR450-MAJOR I-5))
"jmpil$pack @($GRi,$s12)"
(+ pack (misc-null-1) (LI-off) OP_0D GRi s12)
(jump-and-link-semantics GRi s12 LI)
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni callil
"call immediate and link"
- ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6) (FR400-MAJOR I-5))
+ ((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
+ (FR400-MAJOR I-5) (FR450-MAJOR I-5))
"callil$pack @($GRi,$s12)"
(+ pack (misc-null-1) (LI-on) OP_0D GRi s12)
(jump-and-link-semantics GRi s12 LI)
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni call
"call and link"
- ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4) (FR400-MAJOR B-4))
+ ((UNIT B0) (FR500-MAJOR B-4) (FR550-MAJOR B-4)
+ (FR400-MAJOR B-4) (FR450-MAJOR B-4))
"call$pack $label24"
(+ pack OP_0F label24)
(sequence ()
(c-call VOID "@cpu@_set_write_next_vliw_addr_to_LR" 1)
(set pc label24)
(c-call VOID "@cpu@_model_branch" pc #x2)) ; hint branch taken
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni rett
"return from trap"
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2) PRIVILEGED)
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2) PRIVILEGED)
"rett$pack $debug"
(+ pack (misc-null-1) debug OP_05 (rs-null) (s12-null))
; frv_rett handles operating vs user mode
(define-pmacro (trap-r prefix cc i-f op ope cond attr comment)
(dni (.sym prefix cc)
(comment)
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) attr)
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr)
(.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$GRj")
(+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi (misc-null-3) ope GRj)
(trap-semantics (cond (.sym i-f CCi_2)) GRi GRj)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
)
(dni tra
"integer trap always"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1))
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1))
"tra$pack $GRi,$GRj"
(+ pack ICC_ra (ICCi_2-null) OP_04 GRi (misc-null-3) OPE4_0 GRj)
(trap-semantics (const BI 1) GRi GRj)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
(dni tno
"integer trap never"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1))
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1))
"tno$pack"
(+ pack ICC_nev (ICCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_0 (GRj-null))
(trap-semantics (const BI 0) GRi GRj)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
(dni ftra
"float trap always"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS)
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
"ftra$pack $GRi,$GRj"
(+ pack FCC_ra (FCCi_2-null) OP_04 GRi (misc-null-3) OPE4_1 GRj)
(trap-semantics (const BI 1) GRi GRj)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
(dni ftno
"flost trap never"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS)
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
"ftno$pack"
(+ pack FCC_nev (FCCi_2-null) OP_04 (GRi-null) (misc-null-3) OPE4_1 (GRj-null))
(trap-semantics (const BI 0) GRi GRj)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
(define-pmacro (trap-immed prefix cc i-f op cond attr comment)
(dni (.sym prefix cc)
(comment)
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) attr)
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1) attr)
(.str (.sym prefix cc) "$pack $" i-f "CCi_2,$GRi,$s12")
(+ pack (.sym i-f CC_ cc) (.sym i-f CCi_2) op GRi s12)
(trap-semantics (cond (.sym i-f CCi_2)) GRi s12)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
)
(dni tira
"integer trap always"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1))
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1))
"tira$pack $GRi,$s12"
(+ pack ICC_ra (ICCi_2-null) OP_1C GRi s12)
(trap-semantics (const BI 1) GRi s12)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
(dni tino
"integer trap never"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1))
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1))
"tino$pack"
(+ pack ICC_nev (ICCi_2-null) OP_1C (GRi-null) (s12-null))
(trap-semantics (const BI 0) GRi s12)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
(dni ftira
"float trap always"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS)
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
"ftira$pack $GRi,$s12"
(+ pack FCC_ra (ICCi_2-null) OP_1D GRi s12)
(trap-semantics (const BI 1) GRi s12)
(dni ftino
"float trap never"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS)
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
"ftino$pack"
(+ pack FCC_nev (FCCi_2-null) OP_1D (GRi-null) (s12-null))
(trap-semantics (const BI 0) GRi s12)
- ((fr400 (unit u-trap))
+ ((fr400 (unit u-trap)) (fr450 (unit u-trap))
(fr500 (unit u-trap)) (fr550 (unit u-trap)))
)
(dni break
"break trap"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1))
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1))
"break$pack"
(+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_3 (GRj-null))
(sequence ()
(dni mtrap
"media trap"
- ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1) (FR400-MAJOR C-1) FR-ACCESS)
+ ((UNIT C) (FR500-MAJOR C-1) (FR550-MAJOR C-1)
+ (FR400-MAJOR C-1) (FR450-MAJOR C-1) FR-ACCESS)
"mtrap$pack"
(+ pack (rd-null) OP_04 (rs-null) (misc-null-3) OPE4_2 (GRj-null))
(c-call VOID "frv_mtrap")
(define-pmacro (condition-code-logic name operation ope comment)
(dni name
(comment)
- ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) (FR400-MAJOR B-6))
+ ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6)
+ (FR400-MAJOR B-6) (FR450-MAJOR B-6))
(.str name "$pack $CRi,$CRj,$CRk")
(+ pack (misc-null-6) CRk OP_0A (misc-null-7) CRi ope (misc-null-8) CRj)
(set CRk (c-call UQI "@cpu@_cr_logic" operation CRi CRj))
(dni notcr
("not cccr register")
- ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6) (FR400-MAJOR B-6))
+ ((UNIT B01) (FR500-MAJOR B-6) (FR550-MAJOR B-6)
+ (FR400-MAJOR B-6) (FR450-MAJOR B-6))
(.str notcr "$pack $CRj,$CRk")
(+ pack (misc-null-6) CRk OP_0A (rs-null) OPE1_0B (misc-null-8) CRj)
(set CRk (xor CRj 1))
(define-pmacro (check-int-condition-code prefix cc op cond comment)
(dni (.sym prefix cc)
(comment)
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5))
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5))
(.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int")
(+ pack (.sym ICC_ cc) CRj_int op (misc-null-5) ICCi_3)
(check-semantics (cond ICCi_3) CRj_int)
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
)
(dni ckra
"check integer cc always"
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5))
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5))
"ckra$pack $CRj_int"
(+ pack ICC_ra CRj_int OP_08 (misc-null-5) (ICCi_3-null))
(check-semantics (const BI 1) CRj_int)
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
(dni ckno
"check integer cc never"
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5))
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5))
"ckno$pack $CRj_int"
(+ pack ICC_nev CRj_int OP_08 (misc-null-5) (ICCi_3-null))
(check-semantics (const BI 0) CRj_int)
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
(define-pmacro (check-float-condition-code prefix cc op cond comment)
(dni (.sym prefix cc)
(comment)
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS)
(.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float")
(+ pack (.sym FCC_ cc) CRj_float op (misc-null-5) FCCi_3)
(check-semantics (cond FCCi_3) CRj_float)
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
)
(dni fckra
"check float cc always"
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS)
"fckra$pack $CRj_float"
(+ pack FCC_ra CRj_float OP_09 (misc-null-5) FCCi_3)
(check-semantics (const BI 1) CRj_float)
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
(dni fckno
"check float cc never"
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) FR-ACCESS)
"fckno$pack $CRj_float"
(+ pack FCC_nev CRj_float OP_09 (misc-null-5) FCCi_3)
(check-semantics (const BI 0) CRj_float)
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
(define-pmacro (conditional-check-int-condition-code prefix cc op ope test comment)
(dni (.sym prefix cc)
(comment)
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL)
(.str (.sym prefix cc) "$pack $ICCi_3,$CRj_int,$CCi,$cond")
(+ pack (.sym ICC_ cc) CRj_int op (rs-null) CCi cond ope
(misc-null-9) ICCi_3)
(if (eq CCi (or cond 2))
(check-semantics (test ICCi_3) CRj_int)
(set CRj_int (cr-undefined)))
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
)
(dni cckra
"conditional check integer cc always"
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL)
"cckra$pack $CRj_int,$CCi,$cond"
(+ pack ICC_ra CRj_int OP_6A (rs-null) CCi cond OPE4_0
(misc-null-9) (ICCi_3-null))
(if (eq CCi (or cond 2))
(check-semantics (const BI 1) CRj_int)
(set CRj_int (cr-undefined)))
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
(dni cckno
"conditional check integer cc never"
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL)
"cckno$pack $CRj_int,$CCi,$cond"
(+ pack ICC_nev CRj_int OP_6A (rs-null) CCi cond OPE4_0
(misc-null-9) (ICCi_3-null))
(if (eq CCi (or cond 2))
(check-semantics (const BI 0) CRj_int)
(set CRj_int (cr-undefined)))
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
(define-pmacro (conditional-check-float-condition-code prefix cc op ope test comment)
(dni (.sym prefix cc)
(comment)
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS)
(.str (.sym prefix cc) "$pack $FCCi_3,$CRj_float,$CCi,$cond")
(+ pack (.sym FCC_ cc) CRj_float op (rs-null) CCi cond ope
(misc-null-9) FCCi_3)
(if (eq CCi (or cond 2))
(check-semantics (test FCCi_3) CRj_float)
(set CRj_float (cr-undefined)))
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
)
(dni cfckra
"conditional check float cc always"
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS)
"cfckra$pack $CRj_float,$CCi,$cond"
(+ pack FCC_ra CRj_float OP_6A (rs-null) CCi cond OPE4_1
(misc-null-9) (FCCi_3-null))
(if (eq CCi (or cond 2))
(check-semantics (const BI 1) CRj_float)
(set CRj_float (cr-undefined)))
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
(dni cfckno
"conditional check float cc never"
- ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5) (FR400-MAJOR B-5) CONDITIONAL FR-ACCESS)
+ ((UNIT B01) (FR500-MAJOR B-5) (FR550-MAJOR B-5)
+ (FR400-MAJOR B-5) (FR450-MAJOR B-5) CONDITIONAL FR-ACCESS)
"cfckno$pack $CRj_float,$CCi,$cond"
(+ pack FCC_nev CRj_float OP_6A (rs-null) CCi cond OPE4_1
(misc-null-9) (FCCi_3-null))
(if (eq CCi (or cond 2))
(check-semantics (const BI 0) CRj_float)
(set CRj_float (cr-undefined)))
- ((fr400 (unit u-check))
+ ((fr400 (unit u-check)) (fr450 (unit u-check))
(fr500 (unit u-check)) (fr550 (unit u-check)))
)
(dni cjmpl
"conditional jump and link"
((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
- (FR400-MAJOR I-5) CONDITIONAL)
+ (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL)
"cjmpl$pack @($GRi,$GRj),$CCi,$cond"
(+ pack (misc-null-1) (LI-off) OP_6A GRi CCi cond OPE4_2 GRj)
(if (eq CCi (or cond 2))
(jump-and-link-semantics GRi GRj LI))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(dni ccalll
"conditional call and link"
((UNIT I0) (FR500-MAJOR I-5) (FR550-MAJOR I-6)
- (FR400-MAJOR I-5) CONDITIONAL)
+ (FR400-MAJOR I-5) (FR450-MAJOR I-5) CONDITIONAL)
"ccalll$pack @($GRi,$GRj),$CCi,$cond"
(+ pack (misc-null-1) (LI-on) OP_6A GRi CCi cond OPE4_2 GRj)
(if (eq CCi (or cond 2))
(jump-and-link-semantics GRi GRj LI))
- ((fr400 (unit u-branch))
+ ((fr400 (unit u-branch)) (fr450 (unit u-branch))
(fr500 (unit u-branch)) (fr550 (unit u-branch)))
)
(define-pmacro (cache-invalidate name cache all op ope profile comment)
(dni name
(comment)
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2))
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
(.str name "$pack @($GRi,$GRj)")
(+ pack (rd-null) op GRi ope GRj)
(c-call VOID (.str "@cpu@_" cache "_cache_invalidate") (add GRi GRj) all)
)
(cache-invalidate ici insn 0 OP_03 OPE1_38
- ((fr400 (unit u-ici)) (fr500 (unit u-ici)) (fr550 (unit u-ici)))
+ ((fr400 (unit u-ici)) (fr450 (unit u-ici))
+ (fr500 (unit u-ici)) (fr550 (unit u-ici)))
"invalidate insn cache")
(cache-invalidate dci data 0 OP_03 OPE1_3C
- ((fr400 (unit u-dci)) (fr500 (unit u-dci)) (fr550 (unit u-dci)))
+ ((fr400 (unit u-dci)) (fr450 (unit u-dci))
+ (fr500 (unit u-dci)) (fr550 (unit u-dci)))
"invalidate data cache")
(define-pmacro (cache-invalidate-entry name cache op ope profile comment)
(dni name
(comment)
- ((UNIT C) (FR400-MAJOR C-2) (FR550-MAJOR C-2) (MACH fr400,fr550))
+ ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
(.str name "$pack @($GRi,$GRj),$ae")
(+ pack (misc-null-1) ae op GRi ope GRj)
(if (eq ae 0)
)
(cache-invalidate-entry icei insn OP_03 OPE1_39
- ((fr400 (unit u-ici)) (fr550 (unit u-ici)))
+ ((fr400 (unit u-ici)) (fr450 (unit u-ici))
+ (fr550 (unit u-ici)))
"invalidate insn cache entry")
(cache-invalidate-entry dcei data OP_03 OPE1_3A
- ((fr400 (unit u-dci)) (fr550 (unit u-dci)))
+ ((fr400 (unit u-dci)) (fr450 (unit u-dci))
+ (fr550 (unit u-dci)))
"invalidate data cache entry")
(dni dcf
"Data cache flush"
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2))
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
"dcf$pack @($GRi,$GRj)"
(+ pack (rd-null) OP_03 GRi OPE1_3D GRj)
(c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) 0)
- ((fr400 (unit u-dcf))
+ ((fr400 (unit u-dcf)) (fr450 (unit u-dcf))
(fr500 (unit u-dcf)) (fr550 (unit u-dcf)))
)
(dni dcef
"Data cache entry flush"
- ((UNIT C) (FR400-MAJOR C-2) (FR550-MAJOR C-2) (MACH fr400,fr550))
+ ((UNIT C) (MACH fr400,fr450,fr550) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
"dcef$pack @($GRi,$GRj),$ae"
(+ pack (misc-null-1) ae OP_03 GRi OPE1_3B GRj)
(if (eq ae 0)
(c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) -1)
(c-call VOID "@cpu@_data_cache_flush" (add GRi GRj) ae))
- ((fr400 (unit u-dcf)) (fr550 (unit u-dcf)))
+ ((fr400 (unit u-dcf)) (fr450 (unit u-dcf)) (fr550 (unit u-dcf)))
)
(define-pmacro (write-TLB name insn op ope comment)
(define-pmacro (cache-preload name cache pipe attrs op ope profile comment)
(dni name
(comment)
- (.splice (UNIT pipe) (FR500-MAJOR C-2) (FR400-MAJOR C-2) (.unsplice attrs))
+ (.splice (UNIT pipe) (FR500-MAJOR C-2)
+ (FR400-MAJOR C-2) (.unsplice attrs))
(.str name "$pack $GRi,$GRj,$lock")
(+ pack (misc-null-1) lock op GRi ope GRj)
(c-call VOID (.str "@cpu@_" cache "_cache_preload") GRi GRj lock)
)
)
-(cache-preload icpl insn C ((FR550-MAJOR C-2)) OP_03 OPE1_30
- ((fr400 (unit u-icpl)) (fr500 (unit u-icpl)) (fr550 (unit u-icpl)))
+(cache-preload icpl insn C ((FR550-MAJOR C-2) (FR450-MAJOR C-2)) OP_03 OPE1_30
+ ((fr400 (unit u-icpl)) (fr450 (unit u-icpl))
+ (fr500 (unit u-icpl)) (fr550 (unit u-icpl)))
"preload insn cache")
-(cache-preload dcpl data DCPL ((FR550-MAJOR I-8)) OP_03 OPE1_34
- ((fr400 (unit u-dcpl)) (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl)))
+(cache-preload dcpl data DCPL ((FR550-MAJOR I-8) (FR450-MAJOR I-2)) OP_03 OPE1_34
+ ((fr400 (unit u-dcpl)) (fr450 (unit u-dcpl))
+ (fr500 (unit u-dcpl)) (fr550 (unit u-dcpl)))
"preload data cache")
(define-pmacro (cache-unlock name cache op ope profile comment)
(dni name
(comment)
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2))
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
(.str name "$pack $GRi")
(+ pack (rd-null) op GRi ope (GRj-null))
(c-call VOID (.str "@cpu@_" cache "_cache_unlock") GRi)
)
(cache-unlock icul insn OP_03 OPE1_31
- ((fr400 (unit u-icul)) (fr500 (unit u-icul)) (fr550 (unit u-icul)))
+ ((fr400 (unit u-icul)) (fr450 (unit u-icul))
+ (fr500 (unit u-icul)) (fr550 (unit u-icul)))
"unlock insn cache")
(cache-unlock dcul data OP_03 OPE1_35
- ((fr400 (unit u-dcul)) (fr500 (unit u-dcul)) (fr550 (unit u-dcul)))
+ ((fr400 (unit u-dcul)) (fr450 (unit u-dcul))
+ (fr500 (unit u-dcul)) (fr550 (unit u-dcul)))
"unlock data cache")
(define-pmacro (barrier name insn op ope profile comment)
(dni name
(comment)
- ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2) (FR400-MAJOR C-2))
+ ((UNIT C) (FR500-MAJOR C-2) (FR550-MAJOR C-2)
+ (FR400-MAJOR C-2) (FR450-MAJOR C-2))
(.str insn "$pack")
(+ pack (rd-null) op (rs-null) ope (GRj-null))
(nop) ; sufficient implementation
)
(barrier bar bar OP_03 OPE1_3E
- ((fr400 (unit u-barrier)) (fr500 (unit u-barrier)))
+ ((fr400 (unit u-barrier)) (fr450 (unit u-barrier))
+ (fr500 (unit u-barrier)))
"barrier")
(barrier membar membar OP_03 OPE1_3F
- ((fr400 (unit u-membar)) (fr500 (unit u-membar)))
+ ((fr400 (unit u-membar)) (fr450 (unit u-membar))
+ (fr500 (unit u-membar)))
"memory barrier")
+; Load real address instructions
+(define-pmacro (load-real-address name insn what op ope)
+ (dni name
+ (.str "Load real address of " what)
+ ((UNIT C) (FR450-MAJOR C-2) (MACH fr450))
+ (.str insn "$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS")
+ (+ pack GRk op GRi ope LRAE LRAD LRAS (LRA-null))
+ (nop) ; not simulated
+ ()
+ )
+)
+
+(load-real-address lrai "lrai" "instruction" OP_03 OPE1_20)
+(load-real-address lrad "lrad" "data" OP_03 OPE1_21)
+
+(dni tlbpr
+ "TLB Probe"
+ ((UNIT C) (FR450-MAJOR C-2) (MACH fr450))
+ "tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL"
+ (+ pack (TLBPR-null) TLBPRopx TLBPRL OP_03 GRi OPE1_24 GRj)
+ (nop) ; not simulated
+ ()
+)
+
; Coprocessor operations
(define-pmacro (cop-op num op)
(dni (.sym cop num)
(dni mhsetlos
"Media set lower signed 12 bits"
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"mhsetlos$pack $u12,$FRklo"
(+ pack FRklo OP_78 OPE1_20 u12)
(set FRklo u12)
- ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk FRklo))))
+ ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo))
+ (fr550 (unit u-media-set (out FRintk FRklo))))
)
(dni mhsethis
"Media set upper signed 12 bits"
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"mhsethis$pack $u12,$FRkhi"
(+ pack FRkhi OP_78 OPE1_22 u12)
(set FRkhi u12)
- ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk FRkhi))))
+ ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo))
+ (fr550 (unit u-media-set (out FRintk FRkhi))))
)
(dni mhdsets
"Media dual set halfword signed 12 bits"
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"mhdsets$pack $u12,$FRintk"
(+ pack FRintk OP_78 OPE1_24 u12)
(sequence ()
(set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
(set (halfword hi FRintk 0) u12)
(set (halfword lo FRintk 0) u12))
- ((fr400 (unit u-media-1)) (fr550 (unit u-media-set)))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+ (fr550 (unit u-media-set)))
)
(define-pmacro (set-5-semantics target value)
(define-pmacro (media-set-5 name hilo op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
(.str name "$pack $s5,$FRk" hilo)
(+ pack (.sym FRk hilo) op (FRi-null) ope (misc-null-11) s5)
(set-5-semantics (.sym FRk hilo) s5)
- ((fr400 (unit u-media-hilo)) (fr550 (unit u-media-set (out FRintk (.sym FRk hilo)))))
+ ((fr400 (unit u-media-hilo)) (fr450 (unit u-media-hilo))
+ (fr550 (unit u-media-set (out FRintk (.sym FRk hilo)))))
)
)
(dni mhdseth
"Media dual set halfword upper 5 bits"
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-5) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-5)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"mhdseth$pack $s5,$FRintk"
(+ pack FRintk OP_78 (FRi-null) OPE1_25 (misc-null-11) s5)
(sequence ()
(set FRintk (c-raw-call SI "frv_ref_SI" FRintk))
(set-5-semantics (halfword hi FRintk 0) s5)
(set-5-semantics (halfword lo FRintk 0) s5))
- ((fr400 (unit u-media-1)) (fr550 (unit u-media-set)))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+ (fr550 (unit u-media-set)))
)
(define-pmacro (media-logic-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
(.str name "$pack $FRinti,$FRintj,$FRintk")
(+ pack FRintk op FRinti ope FRintj)
(set FRintk (operation FRinti FRintj))
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
)
(define-pmacro (conditional-media-logic name operation op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL)
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL)
(.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond")
(+ pack FRintk op FRinti CCi cond ope FRintj)
(if (eq CCi (or cond 2))
(set FRintk (operation FRinti FRintj)))
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
)
(dni mnot
("mnot")
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
("mnot$pack $FRintj,$FRintk")
(+ pack FRintk OP_7B (rs-null) OPE1_03 FRintj)
(set FRintk (inv FRintj))
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
(dni cmnot
("cmnot")
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL)
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL)
("cmnot$pack $FRintj,$FRintk,$CCi,$cond")
(+ pack FRintk OP_70 (rs-null) CCi cond OPE4_3 FRintj)
(if (eq CCi (or cond 2))
(set FRintk (inv FRintj)))
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
(define-pmacro (media-rotate-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
(.str name "$pack $FRinti,$u6,$FRintk")
(+ pack FRintk op FRinti ope u6)
(set FRintk (operation FRinti (and u6 #x1f)))
- ((fr400 (unit u-media-3))
+ ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
)
(define-pmacro (media-cut-r-r name arg op ope comment)
(dni name
(comment)
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
(.str name "$pack $FRinti,$" arg ",$FRintk")
(+ pack FRintk op FRinti ope arg)
(set FRintk (c-call SI "@cpu@_cut" FRinti (nextreg h-fr_int FRinti 1) arg))
- ((fr400 (unit u-media-3))
+ ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
)
(media-cut-r-r mwcut FRintj OP_7B OPE1_06 "media cut")
(media-cut-r-r mwcuti u6 OP_7B OPE1_07 "media cut")
-(define-pmacro (media-cut-acc name arg op ope comment)
+(define-pmacro (media-cut-acc name arg op ope fr450-major comment)
(dni name
(comment)
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR fr450-major))
(.str name "$pack $ACC40Si,$" arg ",$FRintk")
(+ pack FRintk op ACC40Si ope arg)
(set FRintk (c-call SI "@cpu@_media_cut" ACC40Si arg))
- ((fr400 (unit u-media-4))
+ ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
(fr500 (unit u-media)) (fr550 (unit u-media-3-acc)))
)
)
-(media-cut-acc mcut FRintj OP_7B OPE1_2C "media accumulator cut reg")
-(media-cut-acc mcuti s6 OP_7B OPE1_2E "media accumulator cut immed")
+(media-cut-acc mcut FRintj OP_7B OPE1_2C M-1 "media accumulator cut reg")
+(media-cut-acc mcuti s6 OP_7B OPE1_2E M-5 "media accumulator cut immed")
-(define-pmacro (media-cut-acc-ss name arg op ope comment)
+(define-pmacro (media-cut-acc-ss name arg op ope fr450-major comment)
(dni name
(comment)
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR fr450-major))
(.str name "$pack $ACC40Si,$" arg ",$FRintk")
(+ pack FRintk op ACC40Si ope arg)
(set FRintk (c-call SI "@cpu@_media_cut_ss" ACC40Si arg))
- ((fr400 (unit u-media-4))
+ ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
(fr500 (unit u-media)) (fr550 (unit u-media-3-acc)))
)
)
-(media-cut-acc-ss mcutss FRintj OP_7B OPE1_2D "media accumulator cut reg with saturation")
-(media-cut-acc-ss mcutssi s6 OP_7B OPE1_2F "media accumulator cut immed with saturation")
+(media-cut-acc-ss mcutss FRintj OP_7B OPE1_2D M-1 "media accumulator cut reg with saturation")
+(media-cut-acc-ss mcutssi s6 OP_7B OPE1_2F M-5 "media accumulator cut immed with saturation")
; Dual Media Instructions
;
(dni mdcutssi
"Media dual cut with signed saturation"
- ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT MDCUTSSI) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-6))
"mdcutssi$pack $ACC40Si,$s6,$FRintkeven"
(+ pack FRintkeven OP_78 ACC40Si OPE1_0E s6)
(if (register-unaligned ACC40Si 2)
(c-call SI "@cpu@_media_cut_ss"
(nextreg h-acc40S ACC40Si 1) s6)))))
((fr400 (unit u-media-4-acc-dual
- (out FRintk FRintkeven))) (fr550 (unit u-media-3-acc-dual)))
+ (out FRintk FRintkeven)))
+ (fr450 (unit u-media-4-acc-dual
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-3-acc-dual)))
)
; The (add (xxxx) (mul arg 0)) is a hack to get a reference to arg generated
(dni maveh
"Media dual average"
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"maveh$pack $FRinti,$FRintj,$FRintk"
(+ pack FRintk OP_7B FRinti OPE1_08 FRintj)
(set FRintk (c-call SI "@cpu@_media_average" FRinti FRintj))
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
(define-pmacro (media-dual-shift name operation op ope profile comment)
(dni name
(comment)
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
(.str name "$pack $FRinti,$u6,$FRintk")
(+ pack FRintk op FRinti ope u6)
(sequence ()
)
(media-dual-shift msllhi sll OP_7B OPE1_09
- ((fr400 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media)))
+ ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+ (fr500 (unit u-media)) (fr550 (unit u-media)))
"Media dual shift left logical")
(media-dual-shift msrlhi srl OP_7B OPE1_0A
- ((fr400 (unit u-media-3)) (fr500 (unit u-media)) (fr550 (unit u-media)))
+ ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
+ (fr500 (unit u-media)) (fr550 (unit u-media)))
"Media dual shift right logical")
(media-dual-shift msrahi sra OP_7B OPE1_0B
- ((fr400 (unit u-media-6)) (fr500 (unit u-media)) (fr550 (unit u-media)))
+ ((fr400 (unit u-media-6)) (fr450 (unit u-media-6))
+ (fr500 (unit u-media)) (fr550 (unit u-media)))
"Media dual shift right arithmetic")
(define-pmacro (media-dual-word-rotate-r-r name operation op ope comment)
(dni name
(comment)
- ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
(.str name "$pack $FRintieven,$s6,$FRintkeven")
(+ pack FRintkeven op FRintieven ope s6)
(if (orif (register-unaligned FRintieven 2)
(and s6 #x1f)))))
((fr400 (unit u-media-3-quad
(in FRinti FRintieven)
- (out FRintk FRintkeven))) (fr550 (unit u-media-quad)))
+ (out FRintk FRintkeven)))
+ (fr450 (unit u-media-3-quad
+ (in FRinti FRintieven)
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-quad)))
)
)
(dni mcplhi
"Media bit concatenate, halfword"
- ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
"mcplhi$pack $FRinti,$u6,$FRintk"
(+ pack FRintk OP_78 FRinti OPE1_0C u6)
(sequence ((HI arg1) (HI arg2) (HI shift))
(sub 15 shift)))
(set arg1 (or HI arg1 arg2))))
(set (halfword hi FRintk 0) arg1))
- ((fr400 (unit u-media-3-dual)) (fr550 (unit u-media-3-dual)))
+ ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual))
+ (fr550 (unit u-media-3-dual)))
)
(dni mcpli
"Media bit concatenate, word"
- ((UNIT FMLOW) (MACH fr400,fr550) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FMLOW) (MACH fr400,fr450,fr550) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
"mcpli$pack $FRinti,$u6,$FRintk"
(+ pack FRintk OP_78 FRinti OPE1_0D u6)
(sequence ((SI tmp) (SI shift))
(sub 31 shift)))
(set tmp (or tmp tmp1))))
(set FRintk tmp))
- ((fr400 (unit u-media-3-dual)) (fr550 (unit u-media-3-dual)))
+ ((fr400 (unit u-media-3-dual)) (fr450 (unit u-media-3-dual))
+ (fr550 (unit u-media-3-dual)))
)
(define-pmacro (saturate arg max min result)
(dni msaths
"Media dual saturation signed"
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"msaths$pack $FRinti,$FRintj,$FRintk"
(+ pack FRintk OP_7B FRinti OPE1_0C FRintj)
(sequence ((HI argihi) (HI argilo) (HI argjhi) (HI argjlo))
(extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo)
(saturate argihi argjhi (inv argjhi) (halfword hi FRintk 0))
(saturate argilo argjlo (inv argjlo) (halfword lo FRintk 0)))
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
(dni mqsaths
"Media quad saturation signed"
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-2))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
"mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven"
(+ pack FRintkeven OP_78 FRintieven OPE1_0F FRintjeven)
(if (orif (register-unaligned FRintieven 2)
((fr400 (unit u-media-1-quad
(in FRinti FRintieven)
(in FRintj FRintjeven)
- (out FRintk FRintkeven))) (fr550 (unit u-media-quad)))
+ (out FRintk FRintkeven)))
+ (fr450 (unit u-media-1-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-quad)))
)
(define-pmacro (saturate-unsigned arg max result)
(dni msathu
"Media dual saturation unsigned"
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"msathu$pack $FRinti,$FRintj,$FRintk"
(+ pack FRintk OP_7B FRinti OPE1_0D FRintj)
(sequence ((UHI argihi) (UHI argilo) (UHI argjhi) (UHI argjlo))
(extract-hilo FRinti 0 FRintj 0 argihi argilo argjhi argjlo)
(saturate-unsigned argihi argjhi (halfword hi FRintk 0))
(saturate-unsigned argilo argjlo (halfword lo FRintk 0)))
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
(define-pmacro (media-dual-compare name mode op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
(.str name "$pack $FRinti,$FRintj,$FCCk")
(+ pack (cond-null) FCCk op FRinti ope FRintj)
(if (register-unaligned FCCk 2)
(compare-and-set-fcc argihi argjhi FCCk)
(compare-and-set-fcc argilo argjlo (nextreg h-fccr FCCk 1))))
; TODO - doesn't handle second FCC
- ((fr400 (unit u-media-7))
+ ((fr400 (unit u-media-7)) (fr450 (unit u-media-7))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
)
(dni mabshs
"Media dual absolute value, halfword"
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"mabshs$pack $FRintj,$FRintk"
(+ pack FRintk OP_78 (FRi-null) OPE1_0A FRintj)
(sequence ((HI arghi) (HI arglo))
(halfword hi FRintk 0))
(saturate-v (abs arglo) 32767 -32768 (msr-sie-fri-lo)
(halfword lo FRintk 0)))
- ((fr400 (unit u-media-1)) (fr550 (unit u-media)))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
+ (fr550 (unit u-media)))
)
(define-pmacro (media-arith-sat-semantics
(define-pmacro (media-dual-arith-sat name operation mode max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
(.str name "$pack $FRinti,$FRintj,$FRintk")
(+ pack FRintk op FRinti ope FRintj)
(media-dual-arith-sat-semantics operation mode max min)
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
)
name operation mode max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-1) CONDITIONAL)
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL)
(.str name "$pack $FRinti,$FRintj,$FRintk,$CCi,$cond")
(+ pack FRintk op FRinti CCi cond ope FRintj)
(if (eq CCi (or cond 2))
(media-dual-arith-sat-semantics operation mode max min))
- ((fr400 (unit u-media-1))
+ ((fr400 (unit u-media-1)) (fr450 (unit u-media-1))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
)
(define-pmacro (media-quad-arith-sat name operation mode max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-2))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
(.str name "$pack $FRintieven,$FRintjeven,$FRintkeven")
(+ pack FRintkeven op FRintieven ope FRintjeven)
(media-quad-arith-sat-semantics 1 operation mode max min)
(in FRinti FRintieven)
(in FRintj FRintjeven)
(out FRintk FRintkeven)))
+ (fr450 (unit u-media-1-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)
+ (out FRintk FRintkeven)))
(fr500 (unit u-media-quad-arith
(in FRinti FRintieven)
(in FRintj FRintjeven)
name operation mode max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2) (FR400-MAJOR M-2) CONDITIONAL)
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-2)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL)
(.str name "$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond")
(+ pack FRintkeven op FRintieven CCi cond ope FRintjeven)
(media-quad-arith-sat-semantics (eq CCi (or cond 2))
(in FRinti FRintieven)
(in FRintj FRintjeven)
(out FRintk FRintkeven)))
+ (fr450 (unit u-media-1-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)
+ (out FRintk FRintkeven)))
(fr500 (unit u-media-quad-arith
(in FRinti FRintieven)
(in FRintj FRintjeven)
(conditional-media-quad-arith-sat cmqsubhss sub HI 32767 -32768 OP_73 OPE4_2 "Conditional Media quad sub signed with saturation")
(conditional-media-quad-arith-sat cmqsubhus sub UHI 65535 0 OP_73 OPE4_3 "Conditional Media quad sub unsigned with saturation")
+;; Return A if |A| > |B| and B is positive. Return -A if |A| > |B| and
+;; B is negative, saturating 0x8000 as 0x7fff. Return 0 otherwise.
+(define-pmacro (media-low-clear-semantics a b)
+ (cond HI
+ ((le UHI (abs a) (abs b)) 0)
+ ((le HI 0 b) a)
+ ((eq HI a -32768) 32767)
+ (else (neg a))))
+
+;; Return A if -|B| < A < |B|. Return -B if A <= -|B|, saturating 0x8000
+;; as 0x7fff. Return B if A >= |B|.
+(define-pmacro (media-scope-limit-semantics a b)
+ (cond HI
+ ((andif (gt HI b -32768)
+ (ge HI a (abs b))) b)
+ ((gt HI a (neg (abs b))) a)
+ ((eq HI b -32768) 32767)
+ (else (neg b))))
+
+(define-pmacro (media-quad-limit name operation op ope comment)
+ (dni name
+ comment
+ ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2))
+ (.str name "$pack $FRintieven,$FRintjeven,$FRintkeven")
+ (+ pack FRintkeven op FRintieven ope FRintjeven)
+ (if (orif (register-unaligned FRintieven 2)
+ (orif (register-unaligned FRintjeven 2)
+ (register-unaligned FRintkeven 2)))
+ (c-call VOID "@cpu@_media_register_not_aligned")
+ (sequence ((HI a1) (HI a2) (HI a3) (HI a4)
+ (HI b1) (HI b2) (HI b3) (HI b4))
+ ; hack to get FRintkeven referenced as a target
+ ; for profiling
+ (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+ (extract-hilo FRintieven 0 FRintjeven 0 a1 a2 b1 b2)
+ (extract-hilo FRintieven 1 FRintjeven 1 a3 a4 b3 b4)
+ (set (halfword hi FRintkeven 0) (operation a1 b1))
+ (set (halfword lo FRintkeven 0) (operation a2 b2))
+ (set (halfword hi FRintkeven 1) (operation a3 b3))
+ (set (halfword lo FRintkeven 1) (operation a4 b4))))
+ ((fr450 (unit u-media-1-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)
+ (out FRintk FRintkeven))))
+ )
+)
+
+(media-quad-limit mqlclrhs media-low-clear-semantics OP_78 OPE1_10
+ "Media quad low clear")
+(media-quad-limit mqlmths media-scope-limit-semantics OP_78 OPE1_14
+ "Media quad scope limitation")
+
+(define-pmacro (media-quad-shift name operation op ope comment)
+ (dni name
+ (comment)
+ ((UNIT FM0) (MACH fr450) (FR450-MAJOR M-2))
+ (.str name "$pack $FRintieven,$u6,$FRintkeven")
+ (+ pack FRintkeven op FRintieven ope u6)
+ (if (orif (register-unaligned FRintieven 2)
+ (register-unaligned FRintkeven 2))
+ (c-call VOID "@cpu@_media_register_not_aligned")
+ (sequence ()
+ ; hack to get these referenced for profiling
+ (set FRintieven (c-raw-call SI "frv_ref_SI" FRintieven))
+ (set FRintkeven (c-raw-call SI "frv_ref_SI" FRintkeven))
+ (set (halfword hi FRintkeven 0)
+ (operation HI (halfword hi FRintieven 0)
+ (and u6 #xf)))
+ (set (halfword lo FRintkeven 0)
+ (operation HI (halfword lo FRintieven 0)
+ (and u6 #xf)))
+ (set (halfword hi FRintkeven 1)
+ (operation HI (halfword hi FRintieven 1)
+ (and u6 #xf)))
+ (set (halfword lo FRintkeven 1)
+ (operation HI (halfword lo FRintieven 1)
+ (and u6 #xf)))))
+ ((fr450 (unit u-media-3-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintieven)
+ (out FRintk FRintkeven))))
+ )
+)
+
+(media-quad-shift mqsllhi sll OP_78 OPE1_11 "Media quad left shift")
+(media-quad-shift mqsrahi sra OP_78 OPE1_13 "Media quad right shift")
+
(define-pmacro (media-acc-arith-sat name operation mode max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3))
(.str name "$pack $ACC40Si,$ACC40Sk")
(+ pack ACC40Sk op ACC40Si ope (ACCj-null))
(if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si))
(media-arith-sat-semantics operation ACC40Si
(nextreg h-acc40S ACC40Si 1)
ACC40Sk mode max min (msr-sie-acci)))))
- ((fr400 (unit u-media-2-acc)) (fr550 (unit u-media-4-acc)))
+ ((fr400 (unit u-media-2-acc)) (fr450 (unit u-media-2-acc))
+ (fr550 (unit u-media-4-acc)))
)
)
comment)
(dni name
(comment)
- ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+ ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
(.str name "$pack $ACC40Si,$ACC40Sk")
(+ pack ACC40Sk op ACC40Si ope (ACCj-null))
(if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si))
(nextreg h-acc40S ACC40Sk 1)
mode max min
(msr-sie-acci-1)))))))
- ((fr400 (unit u-media-2-acc-dual)) (fr550 (unit u-media-4-acc-dual)))
+ ((fr400 (unit u-media-2-acc-dual)) (fr450 (unit u-media-2-acc-dual))
+ (fr550 (unit u-media-4-acc-dual)))
)
)
(dni masaccs
"Media add and subtract signed accumulator with saturation"
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3))
"masaccs$pack $ACC40Si,$ACC40Sk"
(+ pack ACC40Sk OP_78 ACC40Si OPE1_08 (ACCj-null))
(if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si))
#x7fffffffff
(inv DI #x7fffffffff)
(msr-sie-acci-1)))))))
- ((fr400 (unit u-media-2-add-sub)) (fr550 (unit u-media-4-add-sub)))
+ ((fr400 (unit u-media-2-add-sub)) (fr450 (unit u-media-2-add-sub))
+ (fr550 (unit u-media-4-add-sub)))
)
(dni mdasaccs
"Media add and subtract signed accumulator with saturation"
- ((UNIT MDUALACC) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+ ((UNIT MDUALACC) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
"mdasaccs$pack $ACC40Si,$ACC40Sk"
(+ pack ACC40Sk OP_78 ACC40Si OPE1_09 (ACCj-null))
(if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Si))
#x7fffffffff
(inv DI #x7fffffffff)
(msr-sie-acci-3)))))))
- ((fr400 (unit u-media-2-add-sub-dual)) (fr550 (unit u-media-4-add-sub-dual)))
+ ((fr400 (unit u-media-2-add-sub-dual))
+ (fr450 (unit u-media-2-add-sub-dual))
+ (fr550 (unit u-media-4-add-sub-dual)))
)
(define-pmacro (media-multiply-semantics conv arg1 arg2 res)
(define-pmacro (media-dual-multiply name mode conv rhs1 rhs2 op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) PRESERVE-OVF)
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3) PRESERVE-OVF)
(.str name "$pack $FRinti,$FRintj,$ACC40Sk")
(+ pack ACC40Sk op FRinti ope FRintj)
(media-dual-multiply-semantics 1 mode conv rhs1 rhs2)
- ((fr400 (unit u-media-2))
+ ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
(fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
)
)
name mode conv rhs1 rhs2 op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1)
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3)
PRESERVE-OVF CONDITIONAL)
(.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond")
(+ pack ACC40Sk op FRinti CCi cond ope FRintj)
(media-dual-multiply-semantics (eq CCi (or cond 2)) mode conv rhs1 rhs2)
- ((fr400 (unit u-media-2))
+ ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
(fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
)
)
(define-pmacro (media-quad-multiply name mode conv rhs1 rhs2 op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) PRESERVE-OVF)
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4) PRESERVE-OVF)
(.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk")
(+ pack ACC40Sk op FRintieven ope FRintjeven)
(media-quad-multiply-semantics 1 mode conv rhs1 rhs2)
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
(in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
(fr500 (unit u-media-quad-mul
(in FRinti FRintieven)
(in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
name mode conv rhs1 rhs2 op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2)
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4)
PRESERVE-OVF CONDITIONAL)
(.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond")
(+ pack ACC40Sk op FRintieven CCi cond ope FRintjeven)
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
(in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
(fr500 (unit u-media-quad-mul
(in FRinti FRintieven)
(in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
name mode conv addop rhw res max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3))
(.str name "$pack $FRinti,$FRintj,$" res)
(+ pack res op FRinti ope FRintj)
(media-dual-multiply-acc-semantics 1 mode conv addop rhw res max min)
- ((fr400 (unit u-media-2))
+ ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
(fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
)
)
name mode conv addop rhw res max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL)
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL)
(.str name "$pack $FRinti,$FRintj,$" res ",$CCi,$cond")
(+ pack res op FRinti CCi cond ope FRintj)
(media-dual-multiply-acc-semantics (eq CCi (or cond 2))
mode conv addop rhw res max min)
- ((fr400 (unit u-media-2))
+ ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
(fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
)
)
name mode conv addop rhw res max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
(.str name "$pack $FRintieven,$FRintjeven,$" res)
(+ pack res op FRintieven ope FRintjeven)
(media-quad-multiply-acc-semantics 1 mode conv addop rhw res max min)
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
(in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
(fr500 (unit u-media-quad-mul
(in FRinti FRintieven)
(in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
name mode conv addop rhw res max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2) CONDITIONAL)
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4) CONDITIONAL)
(.str name "$pack $FRintieven,$FRintjeven,$" res ",$CCi,$cond")
(+ pack res op FRintieven CCi cond ope FRintjeven)
(media-quad-multiply-acc-semantics (eq CCi (or cond 2))
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
(in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
(fr500 (unit u-media-quad-mul
(in FRinti FRintieven)
(in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
name mode conv addop rhw res max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
(.str name "$pack $FRintieven,$FRintjeven,$" res)
(+ pack res op FRintieven ope FRintjeven)
(media-quad-multiply-cross-acc-semantics 1 mode conv addop rhw res
max min)
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
- (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+ (in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
+ (fr550 (unit u-media-4-quad)))
)
)
name mode conv addop rhw res max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
(.str name "$pack $FRintieven,$FRintjeven,$" res)
(+ pack res op FRintieven ope FRintjeven)
(media-quad-cross-multiply-cross-acc-semantics 1 mode conv addop rhw res
max min)
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
- (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+ (in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
+ (fr550 (unit u-media-4-quad)))
)
)
name mode conv addop rhw res max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (MACH fr400,fr550) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+ ((UNIT FMALL) (MACH fr400,fr450,fr550) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
(.str name "$pack $FRintieven,$FRintjeven,$" res)
(+ pack res op FRintieven ope FRintjeven)
(media-quad-cross-multiply-acc-semantics 1 mode conv addop rhw res
max min)
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
- (in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
+ (in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
+ (fr550 (unit u-media-4-quad)))
)
)
name mode conv rhs1 rhs2 max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3))
(.str name "$pack $FRinti,$FRintj,$ACC40Sk")
(+ pack ACC40Sk op FRinti ope FRintj)
(media-dual-complex-semantics mode conv rhs1 rhs2 max min)
- ((fr400 (unit u-media-2))
+ ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
(fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
)
)
name mode conv rhs1 rhs2 max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3))
(.str name "$pack $FRinti,$FRintj,$ACC40Sk")
(+ pack ACC40Sk op FRinti ope FRintj)
(media-dual-complex-semantics-i mode conv rhs1 rhs2 max min)
- ((fr400 (unit u-media-2))
+ ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
(fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
)
)
name mode conv rhs1 rhs2 max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL)
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL)
(.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond")
(+ pack ACC40Sk op FRinti CCi cond ope FRintj)
(if (eq CCi (or cond 2))
(media-dual-complex-semantics mode conv rhs1 rhs2 max min))
- ((fr400 (unit u-media-2))
+ ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
(fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
)
)
name mode conv rhs1 rhs2 max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-1) CONDITIONAL)
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3) CONDITIONAL)
(.str name "$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond")
(+ pack ACC40Sk op FRinti CCi cond ope FRintj)
(if (eq CCi (or cond 2))
(media-dual-complex-semantics-i mode conv rhs1 rhs2 max min))
- ((fr400 (unit u-media-2))
+ ((fr400 (unit u-media-2)) (fr450 (unit u-media-2))
(fr500 (unit u-media-dual-mul)) (fr550 (unit u-media-4)))
)
)
name mode conv rhs1 rhs2 max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
(.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk")
(+ pack ACC40Sk op FRintieven ope FRintjeven)
(if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
(in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
(fr500 (unit u-media-quad-complex
(in FRinti FRintieven)
(in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
name mode conv rhs1 rhs2 max min op ope comment)
(dni name
(comment)
- ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4) (FR400-MAJOR M-2))
+ ((UNIT FMALL) (FR500-MAJOR M-4) (FR550-MAJOR M-4)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
(.str name "$pack $FRintieven,$FRintjeven,$ACC40Sk")
(+ pack ACC40Sk op FRintieven ope FRintjeven)
(if (c-call SI "@cpu@_check_acc_range" (index-of ACC40Sk))
((fr400 (unit u-media-2-quad
(in FRinti FRintieven)
(in FRintj FRintjeven)))
+ (fr450 (unit u-media-2-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)))
(fr500 (unit u-media-quad-complex
(in FRinti FRintieven)
(in FRintj FRintjeven))) (fr550 (unit u-media-4-quad)))
(dni mexpdhw
"Media expand halfword to word"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"mexpdhw$pack $FRinti,$u6,$FRintk"
(+ pack FRintk OP_7B FRinti OPE1_32 u6)
(media-expand-halfword-to-word-semantics 1)
- ((fr400 (unit u-media-3))
+ ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
(dni cmexpdhw
"Conditional media expand halfword to word"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1) CONDITIONAL)
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1) CONDITIONAL)
"cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond"
(+ pack FRintk OP_76 FRinti CCi cond OPE4_2 u6)
(media-expand-halfword-to-word-semantics (eq CCi (or cond 2)))
- ((fr400 (unit u-media-3))
+ ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
(dni mexpdhd
"Media expand halfword to double"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
"mexpdhd$pack $FRinti,$u6,$FRintkeven"
(+ pack FRintkeven OP_7B FRinti OPE1_33 u6)
(media-expand-halfword-to-double-semantics 1)
((fr400 (unit u-media-dual-expand
- (out FRintk FRintkeven)))
+ (out FRintk FRintkeven)))
+ (fr450 (unit u-media-dual-expand
+ (out FRintk FRintkeven)))
(fr500 (unit u-media-dual-expand
- (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand)))
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-dual-expand)))
)
(dni cmexpdhd
"Conditional media expand halfword to double"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL)
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL)
"cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond"
(+ pack FRintkeven OP_76 FRinti CCi cond OPE4_3 u6)
(media-expand-halfword-to-double-semantics (eq CCi (or cond 2)))
((fr400 (unit u-media-dual-expand
(out FRintk FRintkeven)))
+ (fr450 (unit u-media-dual-expand
+ (out FRintk FRintkeven)))
(fr500 (unit u-media-dual-expand
- (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand)))
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-dual-expand)))
)
(dni mpackh
"Media halfword pack"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"mpackh$pack $FRinti,$FRintj,$FRintk"
(+ pack FRintk OP_7B FRinti OPE1_34 FRintj)
(media-pack FRinti FRintj FRintk 0)
- ((fr400 (unit u-media-3))
+ ((fr400 (unit u-media-3)) (fr450 (unit u-media-3))
(fr500 (unit u-media)) (fr550 (unit u-media)))
)
(dni mdpackh
"Media dual pack"
- ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FM01) (FR500-MAJOR M-5) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
"mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven"
(+ pack FRintkeven OP_7B FRintieven OPE1_36 FRintjeven)
(if (orif (register-unaligned FRintieven 2)
(in FRinti FRintieven)
(in FRintj FRintjeven)
(out FRintk FRintkeven)))
+ (fr450 (unit u-media-3-quad
+ (in FRinti FRintieven)
+ (in FRintj FRintjeven)
+ (out FRintk FRintkeven)))
(fr500 (unit u-media-quad-arith
(in FRinti FRintieven)
(in FRintj FRintjeven)
- (out FRintk FRintkeven))) (fr550 (unit u-media-quad)))
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-quad)))
)
(define-pmacro (media-unpack src soff targ toff)
(dni munpackh
"Media halfword unpack"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
"munpackh$pack $FRinti,$FRintkeven"
(+ pack FRintkeven OP_7B FRinti OPE1_35 (FRj-null))
(if (register-unaligned FRintkeven 2)
(media-unpack FRinti 0 FRintkeven 0)))
((fr400 (unit u-media-dual-expand
(out FRintk FRintkeven)))
+ (fr450 (unit u-media-dual-expand
+ (out FRintk FRintkeven)))
(fr500 (unit u-media-dual-expand
- (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand)))
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-dual-expand)))
)
(dni mdunpackh
(dni mbtoh
"Media convert byte to halfword"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
"mbtoh$pack $FRintj,$FRintkeven"
(+ pack FRintkeven OP_7B (FRi-null) OPE1_38 FRintj)
(sequence ()
(mbtoh-semantics 1))
((fr400 (unit u-media-dual-expand
(out FRintk FRintkeven)))
+ (fr450 (unit u-media-dual-expand
+ (out FRintk FRintkeven)))
(fr500 (unit u-media-dual-btoh
- (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand)))
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-dual-expand)))
)
(dni cmbtoh
"Conditional media convert byte to halfword"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL)
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL)
"cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond"
(+ pack FRintkeven OP_77 (FRi-null) CCi cond OPE4_0 FRintj)
(sequence ()
(mbtoh-semantics (eq CCi (or cond 2))))
((fr400 (unit u-media-dual-expand
(out FRintk FRintkeven)))
+ (fr450 (unit u-media-dual-expand
+ (out FRintk FRintkeven)))
(fr500 (unit u-media-dual-btoh
- (out FRintk FRintkeven))) (fr550 (unit u-media-dual-expand (in FRinti FRintj))))
+ (out FRintk FRintkeven)))
+ (fr550 (unit u-media-dual-expand
+ (in FRinti FRintj))))
)
(define-pmacro (mhtob-semantics cond)
(dni mhtob
"Media convert halfword to byte"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2))
"mhtob$pack $FRintjeven,$FRintk"
(+ pack FRintk OP_7B (FRi-null) OPE1_39 FRintjeven)
(sequence ()
(mhtob-semantics 1))
((fr400 (unit u-media-dual-htob
(in FRintj FRintjeven)))
+ (fr450 (unit u-media-dual-htob
+ (in FRintj FRintjeven)))
(fr500 (unit u-media-dual-htob
- (in FRintj FRintjeven))) (fr550 (unit u-media-3-dual (in FRinti FRintjeven))))
+ (in FRintj FRintjeven)))
+ (fr550 (unit u-media-3-dual
+ (in FRinti FRintjeven))))
)
(dni cmhtob
"Conditional media convert halfword to byte"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-2) CONDITIONAL)
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-2) CONDITIONAL)
"cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond"
(+ pack FRintk OP_77 (FRi-null) CCi cond OPE4_1 FRintjeven)
(sequence ()
(mhtob-semantics (eq CCi (or cond 2))))
((fr400 (unit u-media-dual-htob
(in FRintj FRintjeven)))
+ (fr450 (unit u-media-dual-htob
+ (in FRintj FRintjeven)))
(fr500 (unit u-media-dual-htob
- (in FRintj FRintjeven))) (fr550 (unit u-media-3-dual (in FRinti FRintjeven))))
+ (in FRintj FRintjeven)))
+ (fr550 (unit u-media-3-dual
+ (in FRinti FRintjeven))))
)
(define-pmacro (mbtohe-semantics cond)
; Media NOP
; A special case of mclracc
(dni mnop "Media nop"
- ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1) (FR400-MAJOR M-1))
+ ((UNIT FMALL) (FR500-MAJOR M-1) (FR550-MAJOR M-1)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-1))
"mnop$pack"
(+ pack (f-ACC40Sk 63) OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null))
(nop)
; mclracc with #A==0
(dni mclracc-0
"Media clear accumulator(s)"
- ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3))
"mclracc$pack $ACC40Sk,$A0"
(+ pack ACC40Sk OP_7B (f-A 0) (misc-null-10) OPE1_3B (FRj-null))
(c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 0)
- ((fr400 (unit u-media-4))
+ ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
(fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc)))
)
; mclracc with #A==1
(dni mclracc-1
"Media clear accumulator(s)"
- ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3) (FR400-MAJOR M-2))
+ ((UNIT MCLRACC-1) (FR500-MAJOR M-6) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-2) (FR450-MAJOR M-4))
"mclracc$pack $ACC40Sk,$A1"
(+ pack ACC40Sk OP_7B (f-A 1) (misc-null-10) OPE1_3B (FRj-null))
(c-call VOID "@cpu@_clear_accumulators" (index-of ACC40Sk) 1)
- ((fr400 (unit u-media-4))
+ ((fr400 (unit u-media-4)) (fr450 (unit u-media-4-mclracca))
(fr500 (unit u-media)) (fr550 (unit u-media-3-mclracc)))
)
(dni mrdacc
"Media read accumulator"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-5))
"mrdacc$pack $ACC40Si,$FRintk"
(+ pack FRintk OP_7B ACC40Si OPE1_3C (FRj-null))
(set FRintk ACC40Si)
- ((fr400 (unit u-media-4))
+ ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
(fr500 (unit u-media)) (fr550 (unit u-media-3-acc)))
)
(dni mrdaccg
"Media read accumulator guard"
- ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-2) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-5))
"mrdaccg$pack $ACCGi,$FRintk"
(+ pack FRintk OP_7B ACCGi OPE1_3E (FRj-null))
(set FRintk ACCGi)
- ((fr400 (unit u-media-4-accg))
+ ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg))
(fr500 (unit u-media)) (fr550 (unit u-media-3-acc (in ACC40Si ACCGi))))
)
(dni mwtacc
"Media write accumulator"
- ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3))
"mwtacc$pack $FRinti,$ACC40Sk"
(+ pack ACC40Sk OP_7B FRinti OPE1_3D (FRj-null))
(set ACC40Sk (or (and ACC40Sk (const DI #xffffffff00000000))
FRinti))
- ((fr400 (unit u-media-4))
+ ((fr400 (unit u-media-4)) (fr450 (unit u-media-4))
(fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc)))
)
(dni mwtaccg
"Media write accumulator guard"
- ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3) (FR400-MAJOR M-1))
+ ((UNIT FM01) (FR500-MAJOR M-3) (FR550-MAJOR M-3)
+ (FR400-MAJOR M-1) (FR450-MAJOR M-3))
"mwtaccg$pack $FRinti,$ACCGk"
(+ pack ACCGk OP_7B FRinti OPE1_3F (FRj-null))
(sequence ()
; hack to get these referenced for profiling
(c-raw-call VOID "frv_ref_SI" ACCGk)
(set ACCGk FRinti))
- ((fr400 (unit u-media-4-accg))
+ ((fr400 (unit u-media-4-accg)) (fr450 (unit u-media-4-accg))
(fr500 (unit u-media)) (fr550 (unit u-media-3-wtacc (in ACC40Sk ACCGk))))
)
; On the other hand spending a little time in the decoder is often worth it.
;
(dnmi nop "nop"
- ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1))
+ ((UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"nop$pack"
(emit ori pack (GRi 0) (s12 0) (GRk 0))
)
; A return instruction
(dnmi ret "return"
- (NO-DIS (UNIT B01) (FR500-MAJOR B-3) (FR400-MAJOR B-3))
+ (NO-DIS (UNIT B01) (FR500-MAJOR B-3)
+ (FR400-MAJOR B-3) (FR450-MAJOR B-3))
"ret$pack"
(emit bralr pack (hint_taken 2))
)
(dnmi cmp "compare"
- (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1))
+ (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"cmp$pack $GRi,$GRj,$ICCi_1"
(emit subcc pack GRi GRj (GRk 0) ICCi_1)
)
(dnmi cmpi "compare immediate"
- (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1))
+ (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"cmpi$pack $GRi,$s10,$ICCi_1"
(emit subicc pack GRi s10 (GRk 0) ICCi_1)
)
(dnmi ccmp "conditional compare"
- (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"ccmp$pack $GRi,$GRj,$CCi,$cond"
(emit csubcc pack GRi GRj (GRk 0) CCi cond)
)
(dnmi mov "move"
- (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1))
+ (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1))
"mov$pack $GRi,$GRk"
(emit ori pack GRi (s12 0) GRk)
)
(dnmi cmov "conditional move"
- (NO-DIS (UNIT IALL) (FR500-MAJOR I-1) (FR400-MAJOR I-1) CONDITIONAL)
+ (NO-DIS (UNIT IALL) (FR500-MAJOR I-1)
+ (FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"cmov$pack $GRi,$GRk,$CCi,$cond"
(emit cor pack GRi (GRj 0) GRk CCi cond)
)
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr400_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+static int fr450_check_insn_major_constraints
+ PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr500_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr550_check_insn_major_constraints
if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
return 1; /* is a branch */
break;
+ case bfd_mach_fr450:
+ if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
+ return 1; /* is a branch */
+ break;
default:
if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
return 1; /* is a branch */
switch (mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
return 0; /* No float insns */
default:
if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
return 1; /* is a media insn */
break;
+ case bfd_mach_fr450:
+ if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
+ return 1; /* is a media insn */
+ break;
default:
if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
return 1; /* is a media insn */
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
+ if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+ bfd_mach_fr450))
+ return 1;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
+ if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+ bfd_mach_fr450))
+ return 1;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
+ if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+ bfd_mach_fr450))
+ return 1;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
+/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */
+/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
+};
+
+/* Some insns are assigned specialized implementation units which map to
+ different actual implementation units on different machines. These
+ tables perform that mapping. */
+static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
+{
+/* unit in insn actual unit */
+/* NIL */ UNIT_NIL,
+/* I0 */ UNIT_I0,
+/* I1 */ UNIT_I1,
+/* I01 */ UNIT_I01,
+/* I2 */ UNIT_NIL, /* no I2 or I3 unit */
+/* I3 */ UNIT_NIL,
+/* IALL */ UNIT_I01, /* only I0 and I1 units */
+/* FM0 */ UNIT_FM0,
+/* FM1 */ UNIT_FM1,
+/* FM01 */ UNIT_FM01,
+/* FM2 */ UNIT_NIL, /* no F2 or M2 units */
+/* FM3 */ UNIT_NIL, /* no F3 or M3 units */
+/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
+/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
+/* B0 */ UNIT_B0, /* branches only in B0 unit. */
+/* B1 */ UNIT_B0,
+/* B01 */ UNIT_B0,
+/* C */ UNIT_C,
+/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */
+/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */
+/* LOAD */ UNIT_I0, /* load only in I0 unit. */
+/* STORE */ UNIT_I0, /* store only in I0 unit. */
+/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
+/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */
+/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
+/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1. */
/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
};
/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
+/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
/* SCAN */ UNIT_IALL, /* scan in any integer unit. */
/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */
/* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */
+/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
vliw->current_vliw = fr400_allowed_vliw;
vliw->unit_mapping = fr400_unit_mapping;
break;
+ case bfd_mach_fr450:
+ vliw->current_vliw = fr400_allowed_vliw;
+ vliw->unit_mapping = fr450_unit_mapping;
+ break;
case bfd_mach_fr550:
vliw->current_vliw = fr550_allowed_vliw;
vliw->unit_mapping = fr550_unit_mapping;
}
static int
+fr450_check_insn_major_constraints (
+ FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
+)
+{
+ CGEN_ATTR_VALUE_TYPE other_major;
+
+ /* Our caller guarantees there's at least one other instruction. */
+ other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
+
+ /* (M4, M5) and (M4, M6) are allowed. */
+ if (other_major == FR450_MAJOR_M_4)
+ if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
+ return 1;
+
+ /* Otherwise, instructions in even-numbered media categories cannot be
+ executed in parallel with other media instructions. */
+ switch (major)
+ {
+ case FR450_MAJOR_M_2:
+ case FR450_MAJOR_M_4:
+ case FR450_MAJOR_M_6:
+ return !(other_major >= FR450_MAJOR_M_1
+ && other_major <= FR450_MAJOR_M_6);
+
+ case FR450_MAJOR_M_1:
+ case FR450_MAJOR_M_3:
+ case FR450_MAJOR_M_5:
+ return !(other_major == FR450_MAJOR_M_2
+ || other_major == FR450_MAJOR_M_4
+ || other_major == FR450_MAJOR_M_6);
+
+ default:
+ return 1;
+ }
+}
+
+static int
find_unit_in_vliw (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit
)
case bfd_mach_fr400:
rc = fr400_check_insn_major_constraints (vliw, major);
break;
+ case bfd_mach_fr450:
+ rc = fr450_check_insn_major_constraints (vliw, major);
+ break;
case bfd_mach_fr550:
rc = fr550_check_insn_major_constraints (vliw, major, insn);
break;
case bfd_mach_fr400:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
break;
+ case bfd_mach_fr450:
+ major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR);
+ break;
case bfd_mach_fr550:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR);
break;
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
+ * config/tc-frv.c (fr400_audio): New variable.
+ (md_parse_option, md_show_usage): Add -mcpu=fr405 and -mcpu=fr450.
+ (md_parse_option): Set fr400_audio for -mcpu=fr400 and -mcpu=fr405.
+ (target_implements_insn_p): New function.
+ (md_assemble): Report an error if the processor doesn't implement
+ the instruction.
+
2004-02-27 Kazuhiro Inaoka <inaoka.kazuhiro@renesas.com>
* config/tc-m32r.c (md_longopts): Added -no-bitinst option.
#endif
static unsigned long frv_mach = bfd_mach_frv;
+static bfd_boolean fr400_audio;
/* Flags to set in the elf header */
static flagword frv_flags = DEFAULT_FLAGS;
frv_mach = bfd_mach_fr550;
}
+ else if (strcmp (p, "fr450") == 0)
+ {
+ cpu_flags = EF_FRV_CPU_FR450;
+ frv_mach = bfd_mach_fr450;
+ }
+
+ else if (strcmp (p, "fr405") == 0)
+ {
+ cpu_flags = EF_FRV_CPU_FR405;
+ frv_mach = bfd_mach_fr400;
+ fr400_audio = TRUE;
+ }
+
else if (strcmp (p, "fr400") == 0)
{
cpu_flags = EF_FRV_CPU_FR400;
frv_mach = bfd_mach_fr400;
+ fr400_audio = FALSE;
}
else if (strcmp (p, "fr300") == 0)
fprintf (stream, _("-mpic Note small position independent code\n"));
fprintf (stream, _("-mPIC Note large position independent code\n"));
fprintf (stream, _("-mlibrary-pic Compile library for large position indepedent code\n"));
- fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr300|frv|simple|tomcat}\n"));
+ fprintf (stream, _("-mcpu={fr500|fr550|fr400|fr405|fr450|fr300|frv|simple|tomcat}\n"));
fprintf (stream, _(" Record the cpu type\n"));
fprintf (stream, _("-mtomcat-stats Print out stats for tomcat workarounds\n"));
fprintf (stream, _("-mtomcat-debug Debug tomcat workarounds\n"));
return 0; /* all is ok */
}
+/* Return true if the target implements instruction INSN. */
+
+static bfd_boolean
+target_implements_insn_p (const CGEN_INSN *insn)
+{
+ switch (frv_mach)
+ {
+ default:
+ /* bfd_mach_frv or generic. */
+ return TRUE;
+
+ case bfd_mach_fr300:
+ case bfd_mach_frvsimple:
+ return CGEN_INSN_MACH_HAS_P (insn, MACH_SIMPLE);
+
+ case bfd_mach_fr400:
+ return ((fr400_audio || !CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_AUDIO))
+ && CGEN_INSN_MACH_HAS_P (insn, MACH_FR400));
+
+ case bfd_mach_fr450:
+ return CGEN_INSN_MACH_HAS_P (insn, MACH_FR450);
+
+ case bfd_mach_fr500:
+ return CGEN_INSN_MACH_HAS_P (insn, MACH_FR500);
+
+ case bfd_mach_fr550:
+ return CGEN_INSN_MACH_HAS_P (insn, MACH_FR550);
+ }
+}
+
void
md_assemble (str)
char * str;
instructions, don't do vliw checking. */
else if (frv_mach != bfd_mach_frv)
{
+ if (!target_implements_insn_p (insn.insn))
+ {
+ as_bad (_("Instruction not supported by this architecture"));
+ return;
+ }
packing_constraint = frv_vliw_add_insn (& vliw, insn.insn);
if (frv_mach == bfd_mach_fr550 && ! packing_constraint)
packing_constraint = fr550_check_acc_range (& vliw, & insn);
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+ * gas/frv/fr405-insn.[sdl]: New test.
+ * gas/frv/fr450-spr.[sd]: New test.
+ * gas/frv/fr450-insn.[sdl]: New test.
+ * gas/frv/fr450-media-issue.[sl]: New test.
+ * gas/frv/allinsn.exp: Run new tests. Ensure fr405 instructions
+ aren't accepted for -mcpu=fr400 or -mcpu=fr500. Ensure fr450
+ instructions aren't accepted for -mcpu=fr400, -mcpu=fr405 or
+ -mcpu=fr500.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
* gas/frv/allinsn.s (rstb, rsth, rst, rstd, rstq): Replace with nops.
(rstbf, rsthf, rstf, rstdf, rstqf): Likewise.
* gas/frv/allinsn.d: Update accordingly.
# FRV assembler testsuite.
+proc run_list_test { name opts } {
+ global srcdir subdir
+ set testname "$name error test ($opts)"
+ gas_run $name.s $opts >&dump.out
+ if {[regexp_diff dump.out $srcdir/$subdir/$name.l]} {
+ fail $testname
+ verbose "output is [file_contents dump.out]" 2
+ return
+ }
+ pass $testname
+}
+
if [istarget frv*-*-*] {
run_dump_test "allinsn"
run_dump_test "fdpic"
run_dump_test "reloc1"
+ run_dump_test "fr405-insn"
+ run_list_test "fr405-insn" "-mcpu=fr400"
+ run_list_test "fr405-insn" "-mcpu=fr500"
+
+ run_dump_test "fr450-spr"
+ run_dump_test "fr450-insn"
+ run_list_test "fr450-insn" "-mcpu=fr405"
+ run_list_test "fr450-insn" "-mcpu=fr400"
+ run_list_test "fr450-insn" "-mcpu=fr500"
+ run_list_test "fr450-media-issue" "-mcpu=fr450"
}
--- /dev/null
+#as: -mcpu=fr405
+#objdump: -dr
+
+.*: file format elf32-frv
+
+Disassembly of section \.text:
+
+00000000 <.*>:
+.*: 81 18 41 45 smu gr4,gr5
+.*: 81 18 41 85 smass gr4,gr5
+.*: 81 18 41 c5 smsss gr4,gr5
+.*: 8d 18 40 85 slass gr4,gr5,gr6
+.*: 8b 18 01 04 scutss gr4,gr5
+.*: 8d 18 40 05 addss gr4,gr5,gr6
+.*: 8d 18 40 45 subss gr4,gr5,gr6
--- /dev/null
+.*: Assembler messages:
+.*:1: Error: Instruction not supported by this architecture
+.*:2: Error: Instruction not supported by this architecture
+.*:3: Error: Instruction not supported by this architecture
+.*:4: Error: Instruction not supported by this architecture
+.*:5: Error: Instruction not supported by this architecture
+.*:6: Error: Instruction not supported by this architecture
+.*:7: Error: Instruction not supported by this architecture
--- /dev/null
+ smu gr4,gr5
+ smass gr4,gr5
+ smsss gr4,gr5
+ slass gr4,gr5,gr6
+ scutss gr4,gr5
+ addss gr4,gr5,gr6
+ subss gr4,gr5,gr6
--- /dev/null
+#as: -mcpu=fr450
+#objdump: -dr
+
+.*: file format elf32-frv
+
+Disassembly of section \.text:
+
+00000000 <.*>:
+#
+.*: 80 0d f8 00 lrai gr31,gr0,0x0,0x0,0x0
+.*: be 0c 08 00 lrai gr0,gr31,0x0,0x0,0x0
+.*: 80 0c 08 20 lrai gr0,gr0,0x1,0x0,0x0
+.*: 80 0c 08 10 lrai gr0,gr0,0x0,0x1,0x0
+.*: 80 0c 08 08 lrai gr0,gr0,0x0,0x0,0x1
+#
+.*: 80 0d f8 40 lrad gr31,gr0,0x0,0x0,0x0
+.*: be 0c 08 40 lrad gr0,gr31,0x0,0x0,0x0
+.*: 80 0c 08 60 lrad gr0,gr0,0x1,0x0,0x0
+.*: 80 0c 08 50 lrad gr0,gr0,0x0,0x1,0x0
+.*: 80 0c 08 48 lrad gr0,gr0,0x0,0x0,0x1
+#
+.*: 80 0d f9 00 tlbpr gr31,gr0,0x0,0x0
+.*: 80 0c 09 1f tlbpr gr0,gr31,0x0,0x0
+.*: 9c 0c 09 00 tlbpr gr0,gr0,0x7,0x0
+.*: 82 0c 09 00 tlbpr gr0,gr0,0x0,0x1
+#
+.*: 81 e1 e4 00 mqlclrhs fr30,fr0,fr0
+.*: 81 e0 04 1e mqlclrhs fr0,fr30,fr0
+.*: bd e0 04 00 mqlclrhs fr0,fr0,fr30
+#
+.*: 81 e1 e5 00 mqlmths fr30,fr0,fr0
+.*: 81 e0 05 1e mqlmths fr0,fr30,fr0
+.*: bd e0 05 00 mqlmths fr0,fr0,fr30
+#
+.*: 81 e1 e4 40 mqsllhi fr30,0x0,fr0
+.*: 81 e0 04 7f mqsllhi fr0,0x3f,fr0
+.*: bd e0 04 40 mqsllhi fr0,0x0,fr30
+#
+.*: 81 e1 e4 c0 mqsrahi fr30,0x0,fr0
+.*: 81 e0 04 ff mqsrahi fr0,0x3f,fr0
+.*: bd e0 04 c0 mqsrahi fr0,0x0,fr30
--- /dev/null
+.*: Assembler messages:
+.*:1: Error: Instruction not supported by this architecture
+.*:2: Error: Instruction not supported by this architecture
+.*:3: Error: Instruction not supported by this architecture
+.*:4: Error: Instruction not supported by this architecture
+.*:5: Error: Instruction not supported by this architecture
+#
+.*:7: Error: Instruction not supported by this architecture
+.*:8: Error: Instruction not supported by this architecture
+.*:9: Error: Instruction not supported by this architecture
+.*:10: Error: Instruction not supported by this architecture
+.*:11: Error: Instruction not supported by this architecture
+#
+.*:13: Error: Instruction not supported by this architecture
+.*:14: Error: Instruction not supported by this architecture
+.*:15: Error: Instruction not supported by this architecture
+.*:16: Error: Instruction not supported by this architecture
+#
+.*:18: Error: Instruction not supported by this architecture
+.*:19: Error: Instruction not supported by this architecture
+.*:20: Error: Instruction not supported by this architecture
+#
+.*:22: Error: Instruction not supported by this architecture
+.*:23: Error: Instruction not supported by this architecture
+.*:24: Error: Instruction not supported by this architecture
+#
+.*:26: Error: Instruction not supported by this architecture
+.*:27: Error: Instruction not supported by this architecture
+.*:28: Error: Instruction not supported by this architecture
+#
+.*:30: Error: Instruction not supported by this architecture
+.*:31: Error: Instruction not supported by this architecture
+.*:32: Error: Instruction not supported by this architecture
--- /dev/null
+ lrai gr31,gr0,#0,#0,#0
+ lrai gr0,gr31,#0,#0,#0
+ lrai gr0,gr0,#1,#0,#0
+ lrai gr0,gr0,#0,#1,#0
+ lrai gr0,gr0,#0,#0,#1
+
+ lrad gr31,gr0,#0,#0,#0
+ lrad gr0,gr31,#0,#0,#0
+ lrad gr0,gr0,#1,#0,#0
+ lrad gr0,gr0,#0,#1,#0
+ lrad gr0,gr0,#0,#0,#1
+
+ tlbpr gr31,gr0,#0,#0
+ tlbpr gr0,gr31,#0,#0
+ tlbpr gr0,gr0,#7,#0
+ tlbpr gr0,gr0,#0,#1
+
+ mqlclrhs fr30,fr0,fr0
+ mqlclrhs fr0,fr30,fr0
+ mqlclrhs fr0,fr0,fr30
+
+ mqlmths fr30,fr0,fr0
+ mqlmths fr0,fr30,fr0
+ mqlmths fr0,fr0,fr30
+
+ mqsllhi fr30,#0,fr0
+ mqsllhi fr0,#63,fr0
+ mqsllhi fr0,#0,fr30
+
+ mqsrahi fr30,#0,fr0
+ mqsrahi fr0,#63,fr0
+ mqsrahi fr0,#0,fr30
--- /dev/null
+.*: Assembler messages:
+.*:5: Error: VLIW packing constraint violation
+.*:9: Error: VLIW packing constraint violation
+.*:13: Error: VLIW packing constraint violation
+#
+.*:17: Error: VLIW packing constraint violation
+.*:19: Error: VLIW packing constraint violation
+.*:21: Error: VLIW packing constraint violation
+.*:23: Error: VLIW packing constraint violation
+.*:25: Error: VLIW packing constraint violation
+.*:27: Error: VLIW packing constraint violation
+#
+.*:33: Error: VLIW packing constraint violation
+.*:37: Error: VLIW packing constraint violation
+.*:41: Error: VLIW packing constraint violation
+#
+.*:45: Error: VLIW packing constraint violation
+.*:47: Error: VLIW packing constraint violation
+.*:49: Error: VLIW packing constraint violation
+.*:51: Error: VLIW packing constraint violation
+#
+.*:61: Error: VLIW packing constraint violation
+.*:65: Error: VLIW packing constraint violation
+.*:69: Error: VLIW packing constraint violation
+#
+.*:73: Error: VLIW packing constraint violation
+.*:75: Error: VLIW packing constraint violation
+.*:77: Error: VLIW packing constraint violation
+.*:79: Error: VLIW packing constraint violation
+.*:81: Error: VLIW packing constraint violation
+.*:83: Error: VLIW packing constraint violation
--- /dev/null
+ ; M-1 first
+ mand.p fr0,fr1,fr2 ; M1
+ mpackh fr4,fr5,fr6 ; M1 -- ok
+ mand.p fr0,fr1,fr2 ; M1
+ mcpli fr4,#1,fr6 ; M2 -- error
+ mand.p fr0,fr1,fr2 ; M1
+ mmulhu fr4,fr6,acc8 ; M3 -- ok
+ mand.p fr0,fr1,fr2 ; M1
+ mqmulhu fr4,fr6,acc8 ; M4 -- error
+ mand.p fr0,fr1,fr2 ; M1
+ mcuti acc8,#2,fr8 ; M5 -- ok
+ mand.p fr0,fr1,fr2 ; M1
+ mdcutssi acc8,#2,fr8 ; M6 -- error
+
+ ; M-2 first
+ mqaddhss.p fr0,fr2,fr2 ; M2
+ mpackh fr4,fr5,fr6 ; M1 -- error
+ mqaddhss.p fr0,fr2,fr2 ; M2
+ mcpli fr4,#1,fr6 ; M2 -- error
+ mqaddhss.p fr0,fr2,fr2 ; M2
+ mmulhu fr4,fr6,acc8 ; M3 -- error
+ mqaddhss.p fr0,fr2,fr2 ; M2
+ mqmulhu fr4,fr6,acc8 ; M4 -- error
+ mqaddhss.p fr0,fr2,fr2 ; M2
+ mcuti acc8,#2,fr8 ; M5 -- error
+ mqaddhss.p fr0,fr2,fr2 ; M2
+ mdcutssi acc8,#2,fr8 ; M6 -- error
+
+ ; M-3 first
+ mwtacc.p fr0,acc0 ; M3
+ mpackh fr4,fr5,fr6 ; M1 -- ok
+ mwtacc.p fr0,acc0 ; M3
+ mcpli fr4,#1,fr6 ; M2 -- error
+ mwtacc.p fr0,acc0 ; M3
+ mmulhu fr4,fr6,acc8 ; M3 -- ok
+ mwtacc.p fr0,acc0 ; M3
+ mqmulhu fr4,fr6,acc8 ; M4 -- error
+ mwtacc.p fr0,acc0 ; M3
+ mcuti acc8,#2,fr8 ; M5 -- ok
+ mwtacc.p fr0,acc0 ; M3
+ mdcutssi acc8,#2,fr8 ; M6 -- error
+
+ ; M-4 first
+ mqcpxrs.p fr0,fr2,acc0 ; M4
+ mpackh fr4,fr5,fr6 ; M1 -- error
+ mqcpxrs.p fr0,fr2,acc0 ; M4
+ mcpli fr4,#1,fr6 ; M2 -- error
+ mqcpxrs.p fr0,fr2,acc0 ; M4
+ mmulhu fr4,fr6,acc8 ; M3 -- error
+ mqcpxrs.p fr0,fr2,acc0 ; M4
+ mqmulhu fr4,fr6,acc8 ; M4 -- error
+ mqcpxrs.p fr0,fr2,acc0 ; M4
+ mcuti acc8,#2,fr8 ; M5 -- ok
+ mqcpxrs.p fr0,fr2,acc0 ; M4
+ mdcutssi acc8,#2,fr8 ; M6 -- ok
+
+ ; M-5 first
+ mrdacc.p acc0,fr0 ; M5
+ mpackh fr4,fr5,fr6 ; M1 -- ok
+ mrdacc.p acc0,fr0 ; M5
+ mcpli fr4,#1,fr6 ; M2 -- error
+ mrdacc.p acc0,fr0 ; M5
+ mmulhu fr4,fr6,acc8 ; M3 -- ok
+ mrdacc.p acc0,fr0 ; M5
+ mqmulhu fr4,fr6,acc8 ; M4 -- error
+ mrdacc.p acc0,fr0 ; M5
+ mcuti acc8,#2,fr8 ; M5 -- ok
+ mrdacc.p acc0,fr0 ; M5
+ mdcutssi acc8,#2,fr8 ; M6 -- error
+
+ ; M-6 first
+ mdcutssi.p acc0,#3,fr0 ; M6
+ mpackh fr4,fr5,fr6 ; M1 -- error
+ mdcutssi.p acc0,#3,fr0 ; M6
+ mcpli fr4,#1,fr6 ; M2 -- error
+ mdcutssi.p acc0,#3,fr0 ; M6
+ mmulhu fr4,fr6,acc8 ; M3 -- error
+ mdcutssi.p acc0,#3,fr0 ; M6
+ mqmulhu fr4,fr6,acc8 ; M4 -- error
+ mdcutssi.p acc0,#3,fr0 ; M6
+ mcuti acc8,#2,fr8 ; M5 -- error
+ mdcutssi.p acc0,#3,fr0 ; M6
+ mdcutssi acc8,#2,fr8 ; M6 -- error
--- /dev/null
+#as: -mcpu=fr450
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+.* <\.text>:
+.*: 80 0c 01 84 movgs gr4,psr
+.*: 80 0c 11 84 movgs gr4,pcsr
+.*: 80 0c 21 84 movgs gr4,bpcsr
+.*: 80 0c 31 84 movgs gr4,tbr
+.*: 80 0c 41 84 movgs gr4,bpsr
+.*: 80 0d 01 84 movgs gr4,hsr0
+.*: 88 0c 01 84 movgs gr4,ccr
+.*: 88 0c 71 84 movgs gr4,cccr
+.*: 88 0d 01 84 movgs gr4,lr
+.*: 88 0d 11 84 movgs gr4,lcr
+.*: 88 0d 81 84 movgs gr4,iacc0h
+.*: 88 0d 91 84 movgs gr4,iacc0l
+.*: 88 0e 01 84 movgs gr4,isr
+.*: 90 0c 01 84 movgs gr4,epcr0
+.*: 92 0c 01 84 movgs gr4,esr0
+.*: 92 0c e1 84 movgs gr4,esr14
+.*: 92 0c f1 84 movgs gr4,esr15
+.*: 94 0e 11 84 movgs gr4,esfr1
+.*: 9a 0c 01 84 movgs gr4,scr0
+.*: 9a 0c 11 84 movgs gr4,scr1
+.*: 9a 0c 21 84 movgs gr4,scr2
+.*: 9a 0c 31 84 movgs gr4,scr3
+.*: a8 0c 01 84 movgs gr4,msr0
+.*: a8 0c 11 84 movgs gr4,msr1
+.*: b0 0c 01 84 movgs gr4,ear0
+.*: b0 0c f1 84 movgs gr4,ear15
+.*: b4 0c 01 84 movgs gr4,iamlr0
+.*: b4 0c 11 84 movgs gr4,iamlr1
+.*: b4 0c 21 84 movgs gr4,iamlr2
+.*: b4 0c 31 84 movgs gr4,iamlr3
+.*: b4 0c 41 84 movgs gr4,iamlr4
+.*: b4 0c 51 84 movgs gr4,iamlr5
+.*: b4 0c 61 84 movgs gr4,iamlr6
+.*: b4 0c 71 84 movgs gr4,iamlr7
+.*: b6 0c 01 84 movgs gr4,iampr0
+.*: b6 0c 11 84 movgs gr4,iampr1
+.*: b6 0c 21 84 movgs gr4,iampr2
+.*: b6 0c 31 84 movgs gr4,iampr3
+.*: b6 0c 41 84 movgs gr4,iampr4
+.*: b6 0c 51 84 movgs gr4,iampr5
+.*: b6 0c 61 84 movgs gr4,iampr6
+.*: b6 0c 71 84 movgs gr4,iampr7
+.*: b8 0c 01 84 movgs gr4,damlr0
+.*: b8 0c 11 84 movgs gr4,damlr1
+.*: b8 0c 21 84 movgs gr4,damlr2
+.*: b8 0c 31 84 movgs gr4,damlr3
+.*: b8 0c 41 84 movgs gr4,damlr4
+.*: b8 0c 51 84 movgs gr4,damlr5
+.*: b8 0c 61 84 movgs gr4,damlr6
+.*: b8 0c 71 84 movgs gr4,damlr7
+.*: b8 0c 81 84 movgs gr4,damlr8
+.*: b8 0c 91 84 movgs gr4,damlr9
+.*: b8 0c a1 84 movgs gr4,damlr10
+.*: b8 0c b1 84 movgs gr4,damlr11
+.*: ba 0c 01 84 movgs gr4,dampr0
+.*: ba 0c 11 84 movgs gr4,dampr1
+.*: ba 0c 21 84 movgs gr4,dampr2
+.*: ba 0c 31 84 movgs gr4,dampr3
+.*: ba 0c 41 84 movgs gr4,dampr4
+.*: ba 0c 51 84 movgs gr4,dampr5
+.*: ba 0c 61 84 movgs gr4,dampr6
+.*: ba 0c 71 84 movgs gr4,dampr7
+.*: ba 0c 81 84 movgs gr4,dampr8
+.*: ba 0c 91 84 movgs gr4,dampr9
+.*: ba 0c a1 84 movgs gr4,dampr10
+.*: ba 0c b1 84 movgs gr4,dampr11
+.*: bc 0c 01 84 movgs gr4,amcr
+.*: bc 0c 51 84 movgs gr4,iamvr1
+.*: bc 0c 71 84 movgs gr4,damvr1
+.*: bc 0d 01 84 movgs gr4,cxnr
+.*: bc 0d 11 84 movgs gr4,ttbr
+.*: bc 0d 21 84 movgs gr4,tplr
+.*: bc 0d 31 84 movgs gr4,tppr
+.*: bc 0d 41 84 movgs gr4,tpxr
+.*: bc 0e 01 84 movgs gr4,timerh
+.*: bc 0e 11 84 movgs gr4,timerl
+.*: bc 0e 21 84 movgs gr4,timerd
+.*: c0 0c 01 84 movgs gr4,dcr
+.*: c0 0c 11 84 movgs gr4,brr
+.*: c0 0c 21 84 movgs gr4,nmar
+.*: c0 0c 31 84 movgs gr4,btbr
+.*: c0 0c 41 84 movgs gr4,ibar0
+.*: c0 0c 51 84 movgs gr4,ibar1
+.*: c0 0c 61 84 movgs gr4,ibar2
+.*: c0 0c 71 84 movgs gr4,ibar3
+.*: c0 0c 81 84 movgs gr4,dbar0
+.*: c0 0c 91 84 movgs gr4,dbar1
+.*: c0 0c a1 84 movgs gr4,dbar2
+.*: c0 0c b1 84 movgs gr4,dbar3
+.*: c0 0c c1 84 movgs gr4,dbdr00
+.*: c0 0c d1 84 movgs gr4,dbdr01
+.*: c0 0c e1 84 movgs gr4,dbdr02
+.*: c0 0c f1 84 movgs gr4,dbdr03
+.*: c0 0d 01 84 movgs gr4,dbdr10
+.*: c0 0d 11 84 movgs gr4,dbdr11
+.*: c0 0d c1 84 movgs gr4,dbmr00
+.*: c0 0d d1 84 movgs gr4,dbmr01
+.*: c0 0e 01 84 movgs gr4,dbmr10
+.*: c0 0e 11 84 movgs gr4,dbmr11
--- /dev/null
+ movgs gr4, psr ; 0x000 00000
+ movgs gr4, pcsr ; 0x001 00001
+ movgs gr4, bpcsr ; 0x002 00002
+ movgs gr4, tbr ; 0x003 00003
+ movgs gr4, bpsr ; 0x004 00004
+ movgs gr4, hsr0 ; 0x010 00020
+ movgs gr4, ccr ; 0x100 00400
+ movgs gr4, cccr ; 0x107 00407
+ movgs gr4, lr ; 0x110 00420
+ movgs gr4, lcr ; 0x111 00421
+ movgs gr4, iacc0h ; 0x118 00430
+ movgs gr4, iacc0l ; 0x119 00431
+ movgs gr4, isr ; 0x120 00440
+ movgs gr4, epcr0 ; 0x200 01000
+ movgs gr4, esr0 ; 0x240 01100
+ movgs gr4, esr14 ; 0x24e 01116
+ movgs gr4, esr15 ; 0x24f 01117
+ movgs gr4, esfr1 ; 0x2a1 01241
+ movgs gr4, scr0 ; 0x340 01500
+ movgs gr4, scr1 ; 0x341 01501
+ movgs gr4, scr2 ; 0x342 01502
+ movgs gr4, scr3 ; 0x343 01503
+ movgs gr4, msr0 ; 0x500 02400
+ movgs gr4, msr1 ; 0x501 02401
+ movgs gr4, ear0 ; 0x600 03000
+ movgs gr4, ear15 ; 0x60f 03017
+ movgs gr4, iamlr0 ; 0x680 03200
+ movgs gr4, iamlr1 ; 0x681 03201
+ movgs gr4, iamlr2 ; 0x682 03202
+ movgs gr4, iamlr3 ; 0x683 03203
+ movgs gr4, iamlr4 ; 0x684 03204
+ movgs gr4, iamlr5 ; 0x685 03205
+ movgs gr4, iamlr6 ; 0x686 03206
+ movgs gr4, iamlr7 ; 0x687 03207
+ movgs gr4, iampr0 ; 0x6c0 03300
+ movgs gr4, iampr1 ; 0x6c1 03301
+ movgs gr4, iampr2 ; 0x6c2 03302
+ movgs gr4, iampr3 ; 0x6c3 03303
+ movgs gr4, iampr4 ; 0x6c4 03304
+ movgs gr4, iampr5 ; 0x6c5 03305
+ movgs gr4, iampr6 ; 0x6c6 03306
+ movgs gr4, iampr7 ; 0x6c7 03307
+ movgs gr4, damlr0 ; 0x700 03400
+ movgs gr4, damlr1 ; 0x701 03401
+ movgs gr4, damlr2 ; 0x702 03402
+ movgs gr4, damlr3 ; 0x703 03403
+ movgs gr4, damlr4 ; 0x704 03404
+ movgs gr4, damlr5 ; 0x705 03405
+ movgs gr4, damlr6 ; 0x706 03406
+ movgs gr4, damlr7 ; 0x707 03407
+ movgs gr4, damlr8 ; 0x708 03410
+ movgs gr4, damlr9 ; 0x709 03411
+ movgs gr4, damlr10 ; 0x70a 03412
+ movgs gr4, damlr11 ; 0x70b 03413
+ movgs gr4, dampr0 ; 0x740 03500
+ movgs gr4, dampr1 ; 0x741 03501
+ movgs gr4, dampr2 ; 0x742 03502
+ movgs gr4, dampr3 ; 0x743 03503
+ movgs gr4, dampr4 ; 0x744 03504
+ movgs gr4, dampr5 ; 0x745 03505
+ movgs gr4, dampr6 ; 0x746 03506
+ movgs gr4, dampr7 ; 0x747 03507
+ movgs gr4, dampr8 ; 0x748 03510
+ movgs gr4, dampr9 ; 0x749 03511
+ movgs gr4, dampr10 ; 0x74a 03512
+ movgs gr4, dampr11 ; 0x74b 03513
+ movgs gr4, amcr ; 0x780 03600
+ movgs gr4, iamvr1 ; 0x785 03605
+ movgs gr4, damvr1 ; 0x787 03607
+ movgs gr4, cxnr ; 0x790 03620
+ movgs gr4, ttbr ; 0x791 03621
+ movgs gr4, tplr ; 0x792 03622
+ movgs gr4, tppr ; 0x793 03623
+ movgs gr4, tpxr ; 0x794 03624
+ movgs gr4, timerh ; 0x7a0 03640
+ movgs gr4, timerl ; 0x7a1 03641
+ movgs gr4, timerd ; 0x7a2 03642
+ movgs gr4, dcr ; 0x800 04000
+ movgs gr4, brr ; 0x801 04001
+ movgs gr4, nmar ; 0x802 04002
+ movgs gr4, btbr ; 0x803 04003
+ movgs gr4, ibar0 ; 0x804 04004
+ movgs gr4, ibar1 ; 0x805 04005
+ movgs gr4, ibar2 ; 0x806 04006
+ movgs gr4, ibar3 ; 0x807 04007
+ movgs gr4, dbar0 ; 0x808 04010
+ movgs gr4, dbar1 ; 0x809 04011
+ movgs gr4, dbar2 ; 0x80A 04012
+ movgs gr4, dbar3 ; 0x80B 04013
+ movgs gr4, dbdr00 ; 0x80C 04014
+ movgs gr4, dbdr01 ; 0x80D 04015
+ movgs gr4, dbdr02 ; 0x80E 04016
+ movgs gr4, dbdr03 ; 0x80F 04017
+ movgs gr4, dbdr10 ; 0x810 04020
+ movgs gr4, dbdr11 ; 0x811 04021
+ movgs gr4, dbmr00 ; 0x81C 04034
+ movgs gr4, dbmr01 ; 0x81D 04035
+ movgs gr4, dbmr10 ; 0x820 04040
+ movgs gr4, dbmr11 ; 0x821 04041
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
+ * frv.h (EF_FRV_CPU_FR405, EF_FRV_CPU_FR450): Define.
+
2004-01-28 Roland McGrath <roland@redhat.com>
* common.h (AT_SECURE): New macro.
#define EF_FRV_CPU_TOMCAT 0x04000000 /* Tomcat, FR500 prototype */
#define EF_FRV_CPU_FR400 0x05000000 /* FRV400 */
#define EF_FRV_CPU_FR550 0x06000000 /* FRV550 */
+#define EF_FRV_CPU_FR405 0x07000000
+#define EF_FRV_CPU_FR450 0x08000000
/* Mask of PIC related bits */
#define EF_FRV_PIC_FLAGS (EF_FRV_PIC | EF_FRV_LIBPIC | EF_FRV_BIGPIC \
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
+ * ld-frv/fr450-link[abc].s, fr450-link.d: New test.
+ * ld-frv/frv.exp: New harness.
+
2004-02-24 Alexandre Oliva <aoliva@redhat.com>
* ld-frv/fdpic-pie-2.d: Adjust for decay of FUNCDESC relocs that
--- /dev/null
+#source: fr450-linka.s -mcpu=fr400
+#source: fr450-linkb.s -mcpu=fr405
+#source: fr450-linkc.s -mcpu=fr450
+#source: fr450-linkb.s -mcpu=fr405
+#source: fr450-linka.s -mcpu=fr400
+#ld: -r
+#objdump: -p
+
+.*: file format elf32-frv
+private flags = 0x8000000: -mcpu=fr450
+
--- /dev/null
+if [istarget frv*-*-*] {
+ run_dump_test "fr450-link"
+}
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+ * frv-asm.c: Regenerate.
+ * frv-desc.c: Regenerate.
+ * frv-desc.h: Regenerate.
+ * frv-dis.c: Regenerate.
+ * frv-ibld.c: Regenerate.
+ * frv-opc.c: Regenerate.
+ * frv-opc.h: Regenerate.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
* frv-desc.c, frv-opc.c: Regenerate.
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
case FRV_OPERAND_LI :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LI, &fields->f_LI);
break;
+ case FRV_OPERAND_LRAD :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAD, &fields->f_LRAD);
+ break;
+ case FRV_OPERAND_LRAE :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAE, &fields->f_LRAE);
+ break;
+ case FRV_OPERAND_LRAS :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_LRAS, &fields->f_LRAS);
+ break;
+ case FRV_OPERAND_TLBPRL :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPRL, &fields->f_TLBPRL);
+ break;
+ case FRV_OPERAND_TLBPROPX :
+ errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_TLBPROPX, &fields->f_TLBPRopx);
+ break;
case FRV_OPERAND_AE :
errmsg = cgen_parse_unsigned_integer (cd, strp, FRV_OPERAND_AE, &fields->f_ae);
break;
{ "frv", MACH_FRV },
{ "fr550", MACH_FR550 },
{ "fr500", MACH_FR500 },
+ { "fr450", MACH_FR450 },
{ "fr400", MACH_FR400 },
{ "tomcat", MACH_TOMCAT },
{ "simple", MACH_SIMPLE },
{ "SCAN", UNIT_SCAN },
{ "DCPL", UNIT_DCPL },
{ "MDUALACC", UNIT_MDUALACC },
+ { "MDCUTSSI", UNIT_MDCUTSSI },
{ "MCLRACC_1", UNIT_MCLRACC_1 },
{ "NUM_UNITS", UNIT_NUM_UNITS },
{ 0, 0 }
{ 0, 0 }
};
+static const CGEN_ATTR_ENTRY FR450_MAJOR_attr[] =
+{
+ { "NONE", FR450_MAJOR_NONE },
+ { "I_1", FR450_MAJOR_I_1 },
+ { "I_2", FR450_MAJOR_I_2 },
+ { "I_3", FR450_MAJOR_I_3 },
+ { "I_4", FR450_MAJOR_I_4 },
+ { "I_5", FR450_MAJOR_I_5 },
+ { "B_1", FR450_MAJOR_B_1 },
+ { "B_2", FR450_MAJOR_B_2 },
+ { "B_3", FR450_MAJOR_B_3 },
+ { "B_4", FR450_MAJOR_B_4 },
+ { "B_5", FR450_MAJOR_B_5 },
+ { "B_6", FR450_MAJOR_B_6 },
+ { "C_1", FR450_MAJOR_C_1 },
+ { "C_2", FR450_MAJOR_C_2 },
+ { "M_1", FR450_MAJOR_M_1 },
+ { "M_2", FR450_MAJOR_M_2 },
+ { "M_3", FR450_MAJOR_M_3 },
+ { "M_4", FR450_MAJOR_M_4 },
+ { "M_5", FR450_MAJOR_M_5 },
+ { "M_6", FR450_MAJOR_M_6 },
+ { 0, 0 }
+};
+
static const CGEN_ATTR_ENTRY FR500_MAJOR_attr[] =
{
{ "NONE", FR500_MAJOR_NONE },
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "UNIT", & UNIT_attr[0], & UNIT_attr[0] },
{ "FR400-MAJOR", & FR400_MAJOR_attr[0], & FR400_MAJOR_attr[0] },
+ { "FR450-MAJOR", & FR450_MAJOR_attr[0], & FR450_MAJOR_attr[0] },
{ "FR500-MAJOR", & FR500_MAJOR_attr[0], & FR500_MAJOR_attr[0] },
{ "FR550-MAJOR", & FR550_MAJOR_attr[0], & FR550_MAJOR_attr[0] },
{ "ALIAS", &bool_attr[0], &bool_attr[0] },
{ "CONDITIONAL", &bool_attr[0], &bool_attr[0] },
{ "FR-ACCESS", &bool_attr[0], &bool_attr[0] },
{ "PRESERVE-OVF", &bool_attr[0], &bool_attr[0] },
+ { "AUDIO", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
{ "fr500", "fr500", MACH_FR500, 0 },
{ "tomcat", "tomcat", MACH_TOMCAT, 0 },
{ "fr400", "fr400", MACH_FR400, 0 },
+ { "fr450", "fr450", MACH_FR450, 0 },
{ "simple", "simple", MACH_SIMPLE, 0 },
{ 0, 0, 0, 0 }
};
{ "sr1", 769, {0, {0}}, 0, 0 },
{ "sr2", 770, {0, {0}}, 0, 0 },
{ "sr3", 771, {0, {0}}, 0, 0 },
+ { "scr0", 832, {0, {0}}, 0, 0 },
+ { "scr1", 833, {0, {0}}, 0, 0 },
+ { "scr2", 834, {0, {0}}, 0, 0 },
+ { "scr3", 835, {0, {0}}, 0, 0 },
{ "fsr0", 1024, {0, {0}}, 0, 0 },
{ "fsr1", 1025, {0, {0}}, 0, 0 },
{ "fsr2", 1026, {0, {0}}, 0, 0 },
{ "amcr", 1920, {0, {0}}, 0, 0 },
{ "stbar", 1921, {0, {0}}, 0, 0 },
{ "mmcr", 1922, {0, {0}}, 0, 0 },
+ { "iamvr1", 1925, {0, {0}}, 0, 0 },
+ { "damvr1", 1927, {0, {0}}, 0, 0 },
+ { "cxnr", 1936, {0, {0}}, 0, 0 },
+ { "ttbr", 1937, {0, {0}}, 0, 0 },
+ { "tplr", 1938, {0, {0}}, 0, 0 },
+ { "tppr", 1939, {0, {0}}, 0, 0 },
+ { "tpxr", 1940, {0, {0}}, 0, 0 },
+ { "timerh", 1952, {0, {0}}, 0, 0 },
+ { "timerl", 1953, {0, {0}}, 0, 0 },
+ { "timerd", 1954, {0, {0}}, 0, 0 },
{ "dcr", 2048, {0, {0}}, 0, 0 },
{ "brr", 2049, {0, {0}}, 0, 0 },
{ "nmar", 2050, {0, {0}}, 0, 0 },
+ { "btbr", 2051, {0, {0}}, 0, 0 },
{ "ibar0", 2052, {0, {0}}, 0, 0 },
{ "ibar1", 2053, {0, {0}}, 0, 0 },
{ "ibar2", 2054, {0, {0}}, 0, 0 },
CGEN_KEYWORD frv_cgen_opval_spr_names =
{
& frv_cgen_opval_spr_names_entries[0],
- 1007,
+ 1022,
0, 0, 0, 0, ""
};
{ "h-accg", HW_H_ACCG, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_accg_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
{ "h-acc40S", HW_H_ACC40S, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
{ "h-acc40U", HW_H_ACC40U, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_acc_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_BASE) } } },
- { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400) } } },
+ { "h-iacc0", HW_H_IACC0, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iacc0_names, { 0|A(VIRTUAL)|A(PROFILE), { (1<<MACH_FR400)|(1<<MACH_FR450) } } },
{ "h-iccr", HW_H_ICCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_iccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
{ "h-fccr", HW_H_FCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_fccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
{ "h-cccr", HW_H_CCCR, CGEN_ASM_KEYWORD, (PTR) & frv_cgen_opval_cccr_names, { 0|A(PROFILE), { (1<<MACH_BASE) } } },
{ FRV_F_LABELH6, "f-labelH6", 0, 32, 30, 6, { 0, { (1<<MACH_BASE) } } },
{ FRV_F_LABELL18, "f-labelL18", 0, 32, 17, 18, { 0, { (1<<MACH_BASE) } } },
{ FRV_F_LABEL24, "f-label24", 0, 0, 0, 0,{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
+ { FRV_F_LRAE, "f-LRAE", 0, 32, 5, 1, { 0, { (1<<MACH_BASE) } } },
+ { FRV_F_LRAD, "f-LRAD", 0, 32, 4, 1, { 0, { (1<<MACH_BASE) } } },
+ { FRV_F_LRAS, "f-LRAS", 0, 32, 3, 1, { 0, { (1<<MACH_BASE) } } },
+ { FRV_F_TLBPROPX, "f-TLBPRopx", 0, 32, 28, 3, { 0, { (1<<MACH_BASE) } } },
+ { FRV_F_TLBPRL, "f-TLBPRL", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } },
{ FRV_F_ICCI_1_NULL, "f-ICCi_1-null", 0, 32, 11, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
{ FRV_F_ICCI_2_NULL, "f-ICCi_2-null", 0, 32, 26, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
{ FRV_F_ICCI_3_NULL, "f-ICCi_3-null", 0, 32, 1, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
{ FRV_F_MISC_NULL_9, "f-misc-null-9", 0, 32, 5, 4, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
{ FRV_F_MISC_NULL_10, "f-misc-null-10", 0, 32, 16, 5, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
{ FRV_F_MISC_NULL_11, "f-misc-null-11", 0, 32, 5, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
+ { FRV_F_LRA_NULL, "f-LRA-null", 0, 32, 2, 3, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
+ { FRV_F_TLBPR_NULL, "f-TLBPR-null", 0, 32, 30, 2, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
{ FRV_F_LI_OFF, "f-LI-off", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
{ FRV_F_LI_ON, "f-LI-on", 0, 32, 25, 1, { 0|A(RESERVED), { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, 0, {0, {0}} }
{ "label24", FRV_OPERAND_LABEL24, HW_H_IADDR, 17, 24,
{ 2, { (const PTR) &FRV_F_LABEL24_MULTI_IFIELD[0] } },
{ 0|A(PCREL_ADDR)|A(VIRTUAL), { (1<<MACH_BASE) } } },
+/* LRAE: Load Real Address E flag */
+ { "LRAE", FRV_OPERAND_LRAE, HW_H_UINT, 5, 1,
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAE] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* LRAD: Load Real Address D flag */
+ { "LRAD", FRV_OPERAND_LRAD, HW_H_UINT, 4, 1,
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAD] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* LRAS: Load Real Address S flag */
+ { "LRAS", FRV_OPERAND_LRAS, HW_H_UINT, 3, 1,
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_LRAS] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* TLBPRopx: TLB Probe operation number */
+ { "TLBPRopx", FRV_OPERAND_TLBPROPX, HW_H_UINT, 28, 3,
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPROPX] } },
+ { 0, { (1<<MACH_BASE) } } },
+/* TLBPRL: TLB Probe L flag */
+ { "TLBPRL", FRV_OPERAND_TLBPRL, HW_H_UINT, 25, 1,
+ { 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_TLBPRL] } },
+ { 0, { (1<<MACH_BASE) } } },
/* A0: A==0 operand of mclracc */
{ "A0", FRV_OPERAND_A0, HW_H_UINT, 17, 1,
{ 0, { (const PTR) &frv_cgen_ifld_table[FRV_F_A] } },
/* add$pack $GRi,$GRj,$GRk */
{
FRV_INSN_ADD, "add", "add", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* sub$pack $GRi,$GRj,$GRk */
{
FRV_INSN_SUB, "sub", "sub", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* and$pack $GRi,$GRj,$GRk */
{
FRV_INSN_AND, "and", "and", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* or$pack $GRi,$GRj,$GRk */
{
FRV_INSN_OR, "or", "or", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* xor$pack $GRi,$GRj,$GRk */
{
FRV_INSN_XOR, "xor", "xor", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* not$pack $GRj,$GRk */
{
FRV_INSN_NOT, "not", "not", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* sdiv$pack $GRi,$GRj,$GRk */
{
FRV_INSN_SDIV, "sdiv", "sdiv", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* nsdiv$pack $GRi,$GRj,$GRk */
{
FRV_INSN_NSDIV, "nsdiv", "nsdiv", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* udiv$pack $GRi,$GRj,$GRk */
{
FRV_INSN_UDIV, "udiv", "udiv", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* nudiv$pack $GRi,$GRj,$GRk */
{
FRV_INSN_NUDIV, "nudiv", "nudiv", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* smul$pack $GRi,$GRj,$GRdoublek */
{
FRV_INSN_SMUL, "smul", "smul", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* umul$pack $GRi,$GRj,$GRdoublek */
{
FRV_INSN_UMUL, "umul", "umul", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* smu$pack $GRi,$GRj */
{
FRV_INSN_SMU, "smu", "smu", 32,
- { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* smass$pack $GRi,$GRj */
{
FRV_INSN_SMASS, "smass", "smass", 32,
- { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* smsss$pack $GRi,$GRj */
{
FRV_INSN_SMSSS, "smsss", "smsss", 32,
- { 0, { (1<<MACH_FR400), UNIT_IACC, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IACC, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* sll$pack $GRi,$GRj,$GRk */
{
FRV_INSN_SLL, "sll", "sll", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* srl$pack $GRi,$GRj,$GRk */
{
FRV_INSN_SRL, "srl", "srl", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* sra$pack $GRi,$GRj,$GRk */
{
FRV_INSN_SRA, "sra", "sra", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* slass$pack $GRi,$GRj,$GRk */
{
FRV_INSN_SLASS, "slass", "slass", 32,
- { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* scutss$pack $GRj,$GRk */
{
FRV_INSN_SCUTSS, "scutss", "scutss", 32,
- { 0, { (1<<MACH_FR400), UNIT_I0, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_I0, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* scan$pack $GRi,$GRj,$GRk */
{
FRV_INSN_SCAN, "scan", "scan", 32,
- { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* cadd$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CADD, "cadd", "cadd", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csub$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSUB, "csub", "csub", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* cand$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CAND, "cand", "cand", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* cor$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_COR, "cor", "cor", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* cxor$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CXOR, "cxor", "cxor", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* cnot$pack $GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CNOT, "cnot", "cnot", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
{
FRV_INSN_CSMUL, "csmul", "csmul", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSDIV, "csdiv", "csdiv", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CUDIV, "cudiv", "cudiv", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* csll$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSLL, "csll", "csll", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csrl$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSRL, "csrl", "csrl", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csra$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSRA, "csra", "csra", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* cscan$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSCAN, "cscan", "cscan", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* addcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_ADDCC, "addcc", "addcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* subcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_SUBCC, "subcc", "subcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* andcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_ANDCC, "andcc", "andcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* orcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_ORCC, "orcc", "orcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* xorcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_XORCC, "xorcc", "xorcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* sllcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_SLLCC, "sllcc", "sllcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* srlcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_SRLCC, "srlcc", "srlcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* sracc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_SRACC, "sracc", "sracc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* smulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
{
FRV_INSN_SMULCC, "smulcc", "smulcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* umulcc$pack $GRi,$GRj,$GRdoublek,$ICCi_1 */
{
FRV_INSN_UMULCC, "umulcc", "umulcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* caddcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CADDCC, "caddcc", "caddcc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csubcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSUBCC, "csubcc", "csubcc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond */
{
FRV_INSN_CSMULCC, "csmulcc", "csmulcc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* candcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CANDCC, "candcc", "candcc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* corcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CORCC, "corcc", "corcc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* cxorcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CXORCC, "cxorcc", "cxorcc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csllcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSLLCC, "csllcc", "csllcc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csrlcc$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSRLCC, "csrlcc", "csrlcc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* csracc$pack $GRi,$GRj,$GRk,$CCi,$cond */
{
FRV_INSN_CSRACC, "csracc", "csracc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* addx$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_ADDX, "addx", "addx", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* subx$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_SUBX, "subx", "subx", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* addxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_ADDXCC, "addxcc", "addxcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* subxcc$pack $GRi,$GRj,$GRk,$ICCi_1 */
{
FRV_INSN_SUBXCC, "subxcc", "subxcc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* addss$pack $GRi,$GRj,$GRk */
{
FRV_INSN_ADDSS, "addss", "addss", 32,
- { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* subss$pack $GRi,$GRj,$GRk */
{
FRV_INSN_SUBSS, "subss", "subss", 32,
- { 0, { (1<<MACH_FR400), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ { 0|A(AUDIO), { (1<<MACH_FR400)|(1<<MACH_FR450), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* addi$pack $GRi,$s12,$GRk */
{
FRV_INSN_ADDI, "addi", "addi", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* subi$pack $GRi,$s12,$GRk */
{
FRV_INSN_SUBI, "subi", "subi", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* andi$pack $GRi,$s12,$GRk */
{
FRV_INSN_ANDI, "andi", "andi", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* ori$pack $GRi,$s12,$GRk */
{
FRV_INSN_ORI, "ori", "ori", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* xori$pack $GRi,$s12,$GRk */
{
FRV_INSN_XORI, "xori", "xori", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* sdivi$pack $GRi,$s12,$GRk */
{
FRV_INSN_SDIVI, "sdivi", "sdivi", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* nsdivi$pack $GRi,$s12,$GRk */
{
FRV_INSN_NSDIVI, "nsdivi", "nsdivi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* udivi$pack $GRi,$s12,$GRk */
{
FRV_INSN_UDIVI, "udivi", "udivi", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* nudivi$pack $GRi,$s12,$GRk */
{
FRV_INSN_NUDIVI, "nudivi", "nudivi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_MULT_DIV, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* smuli$pack $GRi,$s12,$GRdoublek */
{
FRV_INSN_SMULI, "smuli", "smuli", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* umuli$pack $GRi,$s12,$GRdoublek */
{
FRV_INSN_UMULI, "umuli", "umuli", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* slli$pack $GRi,$s12,$GRk */
{
FRV_INSN_SLLI, "slli", "slli", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* srli$pack $GRi,$s12,$GRk */
{
FRV_INSN_SRLI, "srli", "srli", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* srai$pack $GRi,$s12,$GRk */
{
FRV_INSN_SRAI, "srai", "srai", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* scani$pack $GRi,$s12,$GRk */
{
FRV_INSN_SCANI, "scani", "scani", 32,
- { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_SCAN, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* addicc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_ADDICC, "addicc", "addicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* subicc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_SUBICC, "subicc", "subicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* andicc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_ANDICC, "andicc", "andicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* oricc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_ORICC, "oricc", "oricc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* xoricc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_XORICC, "xoricc", "xoricc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* smulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
{
FRV_INSN_SMULICC, "smulicc", "smulicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* umulicc$pack $GRi,$s10,$GRdoublek,$ICCi_1 */
{
FRV_INSN_UMULICC, "umulicc", "umulicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_MULT_DIV, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_2 } }
},
/* sllicc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_SLLICC, "sllicc", "sllicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* srlicc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_SRLICC, "srlicc", "srlicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* sraicc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_SRAICC, "sraicc", "sraicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* addxi$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_ADDXI, "addxi", "addxi", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* subxi$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_SUBXI, "subxi", "subxi", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* addxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_ADDXICC, "addxicc", "addxicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* subxicc$pack $GRi,$s10,$GRk,$ICCi_1 */
{
FRV_INSN_SUBXICC, "subxicc", "subxicc", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* cmpb$pack $GRi,$GRj,$ICCi_1 */
{
FRV_INSN_CMPB, "cmpb", "cmpb", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
},
/* cmpba$pack $GRi,$GRj,$ICCi_1 */
{
FRV_INSN_CMPBA, "cmpba", "cmpba", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_NONE, FR550_MAJOR_I_1 } }
},
/* setlo$pack $ulo16,$GRklo */
{
FRV_INSN_SETLO, "setlo", "setlo", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* sethi$pack $uhi16,$GRkhi */
{
FRV_INSN_SETHI, "sethi", "sethi", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* setlos$pack $slo16,$GRk */
{
FRV_INSN_SETLOS, "setlos", "setlos", 32,
- { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_I_1 } }
},
/* ldsb$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDSB, "ldsb", "ldsb", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldub$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDUB, "ldub", "ldub", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldsh$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDSH, "ldsh", "ldsh", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lduh$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDUH, "lduh", "lduh", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ld$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LD, "ld", "ld", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldbf$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_LDBF, "ldbf", "ldbf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldhf$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_LDHF, "ldhf", "ldhf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldf$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_LDF, "ldf", "ldf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldc$pack @($GRi,$GRj),$CPRk */
{
FRV_INSN_LDC, "ldc", "ldc", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* nldsb$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDSB, "nldsb", "nldsb", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldub$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDUB, "nldub", "nldub", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldsh$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDSH, "nldsh", "nldsh", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nlduh$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDUH, "nlduh", "nlduh", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nld$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLD, "nld", "nld", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldbf$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_NLDBF, "nldbf", "nldbf", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldhf$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_NLDHF, "nldhf", "nldhf", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldf$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_NLDF, "nldf", "nldf", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldd$pack @($GRi,$GRj),$GRdoublek */
{
FRV_INSN_LDD, "ldd", "ldd", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lddf$pack @($GRi,$GRj),$FRdoublek */
{
FRV_INSN_LDDF, "lddf", "lddf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lddc$pack @($GRi,$GRj),$CPRdoublek */
{
FRV_INSN_LDDC, "lddc", "lddc", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldd$pack @($GRi,$GRj),$GRdoublek */
{
FRV_INSN_NLDD, "nldd", "nldd", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nlddf$pack @($GRi,$GRj),$FRdoublek */
{
FRV_INSN_NLDDF, "nlddf", "nlddf", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldq$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDQ, "ldq", "ldq", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* ldqf$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_LDQF, "ldqf", "ldqf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* ldqc$pack @($GRi,$GRj),$CPRk */
{
FRV_INSN_LDQC, "ldqc", "ldqc", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* nldq$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDQ, "nldq", "nldq", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* nldqf$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_NLDQF, "nldqf", "nldqf", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* ldsbu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDSBU, "ldsbu", "ldsbu", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldubu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDUBU, "ldubu", "ldubu", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldshu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDSHU, "ldshu", "ldshu", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lduhu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDUHU, "lduhu", "lduhu", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDU, "ldu", "ldu", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldsbu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDSBU, "nldsbu", "nldsbu", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldubu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDUBU, "nldubu", "nldubu", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldshu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDSHU, "nldshu", "nldshu", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nlduhu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDUHU, "nlduhu", "nlduhu", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDU, "nldu", "nldu", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldbfu$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_LDBFU, "ldbfu", "ldbfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldhfu$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_LDHFU, "ldhfu", "ldhfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldfu$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_LDFU, "ldfu", "ldfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldcu$pack @($GRi,$GRj),$CPRk */
{
FRV_INSN_LDCU, "ldcu", "ldcu", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* nldbfu$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_NLDBFU, "nldbfu", "nldbfu", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldhfu$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_NLDHFU, "nldhfu", "nldhfu", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldfu$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_NLDFU, "nldfu", "nldfu", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lddu$pack @($GRi,$GRj),$GRdoublek */
{
FRV_INSN_LDDU, "lddu", "lddu", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nlddu$pack @($GRi,$GRj),$GRdoublek */
{
FRV_INSN_NLDDU, "nlddu", "nlddu", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lddfu$pack @($GRi,$GRj),$FRdoublek */
{
FRV_INSN_LDDFU, "lddfu", "lddfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lddcu$pack @($GRi,$GRj),$CPRdoublek */
{
FRV_INSN_LDDCU, "lddcu", "lddcu", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nlddfu$pack @($GRi,$GRj),$FRdoublek */
{
FRV_INSN_NLDDFU, "nlddfu", "nlddfu", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldqu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_LDQU, "ldqu", "ldqu", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* nldqu$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_NLDQU, "nldqu", "nldqu", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* ldqfu$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_LDQFU, "ldqfu", "ldqfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* ldqcu$pack @($GRi,$GRj),$CPRk */
{
FRV_INSN_LDQCU, "ldqcu", "ldqcu", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* nldqfu$pack @($GRi,$GRj),$FRintk */
{
FRV_INSN_NLDQFU, "nldqfu", "nldqfu", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* ldsbi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_LDSBI, "ldsbi", "ldsbi", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldshi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_LDSHI, "ldshi", "ldshi", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_LDI, "ldi", "ldi", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldubi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_LDUBI, "ldubi", "ldubi", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lduhi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_LDUHI, "lduhi", "lduhi", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldbfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_LDBFI, "ldbfi", "ldbfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldhfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_LDHFI, "ldhfi", "ldhfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_LDFI, "ldfi", "ldfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldsbi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_NLDSBI, "nldsbi", "nldsbi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldubi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_NLDUBI, "nldubi", "nldubi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldshi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_NLDSHI, "nldshi", "nldshi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nlduhi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_NLDUHI, "nlduhi", "nlduhi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_NLDI, "nldi", "nldi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldbfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_NLDBFI, "nldbfi", "nldbfi", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldhfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_NLDHFI, "nldhfi", "nldhfi", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nldfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_NLDFI, "nldfi", "nldfi", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lddi$pack @($GRi,$d12),$GRdoublek */
{
FRV_INSN_LDDI, "lddi", "lddi", 32,
- { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* lddfi$pack @($GRi,$d12),$FRdoublek */
{
FRV_INSN_LDDFI, "lddfi", "lddfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nlddi$pack @($GRi,$d12),$GRdoublek */
{
FRV_INSN_NLDDI, "nlddi", "nlddi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* nlddfi$pack @($GRi,$d12),$FRdoublek */
{
FRV_INSN_NLDDFI, "nlddfi", "nlddfi", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* ldqi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_LDQI, "ldqi", "ldqi", 32,
- { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* ldqfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_LDQFI, "ldqfi", "ldqfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* nldqfi$pack @($GRi,$d12),$FRintk */
{
FRV_INSN_NLDQFI, "nldqfi", "nldqfi", 32,
- { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS)|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* stb$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_STB, "stb", "stb", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* sth$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_STH, "sth", "sth", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* st$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_ST, "st", "st", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stbf$pack $FRintk,@($GRi,$GRj) */
{
FRV_INSN_STBF, "stbf", "stbf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* sthf$pack $FRintk,@($GRi,$GRj) */
{
FRV_INSN_STHF, "sthf", "sthf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stf$pack $FRintk,@($GRi,$GRj) */
{
FRV_INSN_STF, "stf", "stf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stc$pack $CPRk,@($GRi,$GRj) */
{
FRV_INSN_STC, "stc", "stc", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* std$pack $GRdoublek,@($GRi,$GRj) */
{
FRV_INSN_STD, "std", "std", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stdf$pack $FRdoublek,@($GRi,$GRj) */
{
FRV_INSN_STDF, "stdf", "stdf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stdc$pack $CPRdoublek,@($GRi,$GRj) */
{
FRV_INSN_STDC, "stdc", "stdc", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stq$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_STQ, "stq", "stq", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* stqf$pack $FRintk,@($GRi,$GRj) */
{
FRV_INSN_STQF, "stqf", "stqf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* stqc$pack $CPRk,@($GRi,$GRj) */
{
FRV_INSN_STQC, "stqc", "stqc", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* stbu$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_STBU, "stbu", "stbu", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* sthu$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_STHU, "sthu", "sthu", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stu$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_STU, "stu", "stu", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stbfu$pack $FRintk,@($GRi,$GRj) */
{
FRV_INSN_STBFU, "stbfu", "stbfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* sthfu$pack $FRintk,@($GRi,$GRj) */
{
FRV_INSN_STHFU, "sthfu", "sthfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stfu$pack $FRintk,@($GRi,$GRj) */
{
FRV_INSN_STFU, "stfu", "stfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stcu$pack $CPRk,@($GRi,$GRj) */
{
FRV_INSN_STCU, "stcu", "stcu", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stdu$pack $GRdoublek,@($GRi,$GRj) */
{
FRV_INSN_STDU, "stdu", "stdu", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stdfu$pack $FRdoublek,@($GRi,$GRj) */
{
FRV_INSN_STDFU, "stdfu", "stdfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stdcu$pack $CPRdoublek,@($GRi,$GRj) */
{
FRV_INSN_STDCU, "stdcu", "stdcu", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stqu$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_STQU, "stqu", "stqu", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* stqfu$pack $FRintk,@($GRi,$GRj) */
{
FRV_INSN_STQFU, "stqfu", "stqfu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* stqcu$pack $CPRk,@($GRi,$GRj) */
{
FRV_INSN_STQCU, "stqcu", "stqcu", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* cldsb$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDSB, "cldsb", "cldsb", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldub$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDUB, "cldub", "cldub", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldsh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDSH, "cldsh", "cldsh", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* clduh$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDUH, "clduh", "clduh", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cld$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLD, "cld", "cld", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldbf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
{
FRV_INSN_CLDBF, "cldbf", "cldbf", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldhf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
{
FRV_INSN_CLDHF, "cldhf", "cldhf", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldf$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
{
FRV_INSN_CLDF, "cldf", "cldf", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldd$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
{
FRV_INSN_CLDD, "cldd", "cldd", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* clddf$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
{
FRV_INSN_CLDDF, "clddf", "clddf", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldq$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDQ, "cldq", "cldq", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* cldsbu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDSBU, "cldsbu", "cldsbu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldubu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDUBU, "cldubu", "cldubu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldshu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDSHU, "cldshu", "cldshu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* clduhu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDUHU, "clduhu", "clduhu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDU, "cldu", "cldu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldbfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
{
FRV_INSN_CLDBFU, "cldbfu", "cldbfu", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldhfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
{
FRV_INSN_CLDHFU, "cldhfu", "cldhfu", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldfu$pack @($GRi,$GRj),$FRintk,$CCi,$cond */
{
FRV_INSN_CLDFU, "cldfu", "cldfu", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* clddu$pack @($GRi,$GRj),$GRdoublek,$CCi,$cond */
{
FRV_INSN_CLDDU, "clddu", "clddu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* clddfu$pack @($GRi,$GRj),$FRdoublek,$CCi,$cond */
{
FRV_INSN_CLDDFU, "clddfu", "clddfu", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_LOAD, FR400_MAJOR_I_2, FR450_MAJOR_I_2, FR500_MAJOR_I_2, FR550_MAJOR_I_3 } }
},
/* cldqu$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CLDQU, "cldqu", "cldqu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
+ { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_LOAD, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_2, FR550_MAJOR_NONE } }
},
/* cstb$pack $GRk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTB, "cstb", "cstb", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* csth$pack $GRk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTH, "csth", "csth", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cst$pack $GRk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CST, "cst", "cst", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstbf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTBF, "cstbf", "cstbf", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* csthf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTHF, "csthf", "csthf", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstf$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTF, "cstf", "cstf", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstd$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTD, "cstd", "cstd", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstdf$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTDF, "cstdf", "cstdf", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstq$pack $GRk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTQ, "cstq", "cstq", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* cstbu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTBU, "cstbu", "cstbu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* csthu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTHU, "csthu", "csthu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstu$pack $GRk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTU, "cstu", "cstu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstbfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTBFU, "cstbfu", "cstbfu", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* csthfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTHFU, "csthfu", "csthfu", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstfu$pack $FRintk,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTFU, "cstfu", "cstfu", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstdu$pack $GRdoublek,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTDU, "cstdu", "cstdu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* cstdfu$pack $FRdoublek,@($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CSTDFU, "cstdfu", "cstdfu", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stbi$pack $GRk,@($GRi,$d12) */
{
FRV_INSN_STBI, "stbi", "stbi", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* sthi$pack $GRk,@($GRi,$d12) */
{
FRV_INSN_STHI, "sthi", "sthi", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* sti$pack $GRk,@($GRi,$d12) */
{
FRV_INSN_STI, "sti", "sti", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stbfi$pack $FRintk,@($GRi,$d12) */
{
FRV_INSN_STBFI, "stbfi", "stbfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* sthfi$pack $FRintk,@($GRi,$d12) */
{
FRV_INSN_STHFI, "sthfi", "sthfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stfi$pack $FRintk,@($GRi,$d12) */
{
FRV_INSN_STFI, "stfi", "stfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stdi$pack $GRdoublek,@($GRi,$d12) */
{
FRV_INSN_STDI, "stdi", "stdi", 32,
- { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stdfi$pack $FRdoublek,@($GRi,$d12) */
{
FRV_INSN_STDFI, "stdfi", "stdfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_STORE, FR400_MAJOR_I_3, FR450_MAJOR_I_3, FR500_MAJOR_I_3, FR550_MAJOR_I_4 } }
},
/* stqi$pack $GRk,@($GRi,$d12) */
{
FRV_INSN_STQI, "stqi", "stqi", 32,
- { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* stqfi$pack $FRintk,@($GRi,$d12) */
{
FRV_INSN_STQFI, "stqfi", "stqfi", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_STORE, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_3, FR550_MAJOR_NONE } }
},
/* swap$pack @($GRi,$GRj),$GRk */
{
FRV_INSN_SWAP, "swap", "swap", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* swapi$pack @($GRi,$d12),$GRk */
{
FRV_INSN_SWAPI, "swapi", "swapi", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* cswap$pack @($GRi,$GRj),$GRk,$CCi,$cond */
{
FRV_INSN_CSWAP, "cswap", "cswap", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* movgf$pack $GRj,$FRintk */
{
FRV_INSN_MOVGF, "movgf", "movgf", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
},
/* movfg$pack $FRintk,$GRj */
{
FRV_INSN_MOVFG, "movfg", "movfg", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
},
/* movgfd$pack $GRj,$FRintk */
{
FRV_INSN_MOVGFD, "movgfd", "movgfd", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
},
/* movfgd$pack $FRintk,$GRj */
{
FRV_INSN_MOVFGD, "movfgd", "movfgd", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
},
/* movgfq$pack $GRj,$FRintk */
{
FRV_INSN_MOVGFQ, "movgfq", "movgfq", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
},
/* movfgq$pack $FRintk,$GRj */
{
FRV_INSN_MOVFGQ, "movfgq", "movfgq", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV), UNIT_I0, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_4, FR550_MAJOR_NONE } }
},
/* cmovgf$pack $GRj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMOVGF, "cmovgf", "cmovgf", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
},
/* cmovfg$pack $FRintk,$GRj,$CCi,$cond */
{
FRV_INSN_CMOVFG, "cmovfg", "cmovfg", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
},
/* cmovgfd$pack $GRj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMOVGFD, "cmovgfd", "cmovgfd", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
},
/* cmovfgd$pack $FRintk,$GRj,$CCi,$cond */
{
FRV_INSN_CMOVFGD, "cmovfgd", "cmovfgd", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_4, FR450_MAJOR_I_4, FR500_MAJOR_I_4, FR550_MAJOR_I_5 } }
},
/* movgs$pack $GRj,$spr */
{
FRV_INSN_MOVGS, "movgs", "movgs", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* movsg$pack $spr,$GRj */
{
FRV_INSN_MOVSG, "movsg", "movsg", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* bra$pack $hint_taken$label16 */
{
FRV_INSN_BRA, "bra", "bra", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bno$pack$hint_not_taken */
{
FRV_INSN_BNO, "bno", "bno", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* beq$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BEQ, "beq", "beq", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bne$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BNE, "bne", "bne", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* ble$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BLE, "ble", "ble", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bgt$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BGT, "bgt", "bgt", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* blt$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BLT, "blt", "blt", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bge$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BGE, "bge", "bge", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bls$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BLS, "bls", "bls", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bhi$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BHI, "bhi", "bhi", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bc$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BC, "bc", "bc", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bnc$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BNC, "bnc", "bnc", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bn$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BN, "bn", "bn", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bp$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BP, "bp", "bp", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bv$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BV, "bv", "bv", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bnv$pack $ICCi_2,$hint,$label16 */
{
FRV_INSN_BNV, "bnv", "bnv", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbra$pack $hint_taken$label16 */
{
FRV_INSN_FBRA, "fbra", "fbra", 32,
- { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbno$pack$hint_not_taken */
{
FRV_INSN_FBNO, "fbno", "fbno", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbne$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBNE, "fbne", "fbne", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbeq$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBEQ, "fbeq", "fbeq", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fblg$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBLG, "fblg", "fblg", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbue$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBUE, "fbue", "fbue", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbul$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBUL, "fbul", "fbul", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbge$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBGE, "fbge", "fbge", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fblt$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBLT, "fblt", "fblt", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbuge$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBUGE, "fbuge", "fbuge", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbug$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBUG, "fbug", "fbug", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fble$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBLE, "fble", "fble", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbgt$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBGT, "fbgt", "fbgt", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbule$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBULE, "fbule", "fbule", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbu$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBU, "fbu", "fbu", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* fbo$pack $FCCi_2,$hint,$label16 */
{
FRV_INSN_FBO, "fbo", "fbo", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_1, FR450_MAJOR_B_1, FR500_MAJOR_B_1, FR550_MAJOR_B_1 } }
},
/* bctrlr$pack $ccond,$hint */
{
FRV_INSN_BCTRLR, "bctrlr", "bctrlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bralr$pack$hint_taken */
{
FRV_INSN_BRALR, "bralr", "bralr", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bnolr$pack$hint_not_taken */
{
FRV_INSN_BNOLR, "bnolr", "bnolr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* beqlr$pack $ICCi_2,$hint */
{
FRV_INSN_BEQLR, "beqlr", "beqlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bnelr$pack $ICCi_2,$hint */
{
FRV_INSN_BNELR, "bnelr", "bnelr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* blelr$pack $ICCi_2,$hint */
{
FRV_INSN_BLELR, "blelr", "blelr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bgtlr$pack $ICCi_2,$hint */
{
FRV_INSN_BGTLR, "bgtlr", "bgtlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bltlr$pack $ICCi_2,$hint */
{
FRV_INSN_BLTLR, "bltlr", "bltlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bgelr$pack $ICCi_2,$hint */
{
FRV_INSN_BGELR, "bgelr", "bgelr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* blslr$pack $ICCi_2,$hint */
{
FRV_INSN_BLSLR, "blslr", "blslr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bhilr$pack $ICCi_2,$hint */
{
FRV_INSN_BHILR, "bhilr", "bhilr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bclr$pack $ICCi_2,$hint */
{
FRV_INSN_BCLR, "bclr", "bclr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bnclr$pack $ICCi_2,$hint */
{
FRV_INSN_BNCLR, "bnclr", "bnclr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bnlr$pack $ICCi_2,$hint */
{
FRV_INSN_BNLR, "bnlr", "bnlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bplr$pack $ICCi_2,$hint */
{
FRV_INSN_BPLR, "bplr", "bplr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bvlr$pack $ICCi_2,$hint */
{
FRV_INSN_BVLR, "bvlr", "bvlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bnvlr$pack $ICCi_2,$hint */
{
FRV_INSN_BNVLR, "bnvlr", "bnvlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbralr$pack$hint_taken */
{
FRV_INSN_FBRALR, "fbralr", "fbralr", 32,
- { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbnolr$pack$hint_not_taken */
{
FRV_INSN_FBNOLR, "fbnolr", "fbnolr", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbeqlr$pack $FCCi_2,$hint */
{
FRV_INSN_FBEQLR, "fbeqlr", "fbeqlr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbnelr$pack $FCCi_2,$hint */
{
FRV_INSN_FBNELR, "fbnelr", "fbnelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fblglr$pack $FCCi_2,$hint */
{
FRV_INSN_FBLGLR, "fblglr", "fblglr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbuelr$pack $FCCi_2,$hint */
{
FRV_INSN_FBUELR, "fbuelr", "fbuelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbullr$pack $FCCi_2,$hint */
{
FRV_INSN_FBULLR, "fbullr", "fbullr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbgelr$pack $FCCi_2,$hint */
{
FRV_INSN_FBGELR, "fbgelr", "fbgelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbltlr$pack $FCCi_2,$hint */
{
FRV_INSN_FBLTLR, "fbltlr", "fbltlr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbugelr$pack $FCCi_2,$hint */
{
FRV_INSN_FBUGELR, "fbugelr", "fbugelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbuglr$pack $FCCi_2,$hint */
{
FRV_INSN_FBUGLR, "fbuglr", "fbuglr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fblelr$pack $FCCi_2,$hint */
{
FRV_INSN_FBLELR, "fblelr", "fblelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbgtlr$pack $FCCi_2,$hint */
{
FRV_INSN_FBGTLR, "fbgtlr", "fbgtlr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbulelr$pack $FCCi_2,$hint */
{
FRV_INSN_FBULELR, "fbulelr", "fbulelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbulr$pack $FCCi_2,$hint */
{
FRV_INSN_FBULR, "fbulr", "fbulr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* fbolr$pack $FCCi_2,$hint */
{
FRV_INSN_FBOLR, "fbolr", "fbolr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_B_3 } }
},
/* bcralr$pack $ccond$hint_taken */
{
FRV_INSN_BCRALR, "bcralr", "bcralr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcnolr$pack$hint_not_taken */
{
FRV_INSN_BCNOLR, "bcnolr", "bcnolr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bceqlr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCEQLR, "bceqlr", "bceqlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcnelr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCNELR, "bcnelr", "bcnelr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bclelr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCLELR, "bclelr", "bclelr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcgtlr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCGTLR, "bcgtlr", "bcgtlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcltlr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCLTLR, "bcltlr", "bcltlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcgelr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCGELR, "bcgelr", "bcgelr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bclslr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCLSLR, "bclslr", "bclslr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bchilr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCHILR, "bchilr", "bchilr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcclr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCCLR, "bcclr", "bcclr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcnclr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCNCLR, "bcnclr", "bcnclr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcnlr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCNLR, "bcnlr", "bcnlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcplr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCPLR, "bcplr", "bcplr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcvlr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCVLR, "bcvlr", "bcvlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* bcnvlr$pack $ICCi_2,$ccond,$hint */
{
FRV_INSN_BCNVLR, "bcnvlr", "bcnvlr", 32,
- { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbralr$pack $ccond$hint_taken */
{
FRV_INSN_FCBRALR, "fcbralr", "fcbralr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbnolr$pack$hint_not_taken */
{
FRV_INSN_FCBNOLR, "fcbnolr", "fcbnolr", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbeqlr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBEQLR, "fcbeqlr", "fcbeqlr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbnelr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBNELR, "fcbnelr", "fcbnelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcblglr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBLGLR, "fcblglr", "fcblglr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbuelr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBUELR, "fcbuelr", "fcbuelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbullr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBULLR, "fcbullr", "fcbullr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbgelr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBGELR, "fcbgelr", "fcbgelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbltlr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBLTLR, "fcbltlr", "fcbltlr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbugelr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBUGELR, "fcbugelr", "fcbugelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbuglr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBUGLR, "fcbuglr", "fcbuglr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcblelr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBLELR, "fcblelr", "fcblelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbgtlr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBGTLR, "fcbgtlr", "fcbgtlr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbulelr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBULELR, "fcbulelr", "fcbulelr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbulr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBULR, "fcbulr", "fcbulr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* fcbolr$pack $FCCi_2,$ccond,$hint */
{
FRV_INSN_FCBOLR, "fcbolr", "fcbolr", 32,
- { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
+ { 0|A(FR_ACCESS)|A(COND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_2, FR450_MAJOR_B_2, FR500_MAJOR_B_2, FR550_MAJOR_B_2 } }
},
/* jmpl$pack @($GRi,$GRj) */
{
FRV_INSN_JMPL, "jmpl", "jmpl", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
},
/* calll$pack @($GRi,$GRj) */
{
FRV_INSN_CALLL, "calll", "calll", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
},
/* jmpil$pack @($GRi,$s12) */
{
FRV_INSN_JMPIL, "jmpil", "jmpil", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
},
/* callil$pack @($GRi,$s12) */
{
FRV_INSN_CALLIL, "callil", "callil", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
},
/* call$pack $label24 */
{
FRV_INSN_CALL, "call", "call", 32,
- { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR500_MAJOR_B_4, FR550_MAJOR_B_4 } }
+ { 0|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_B0, FR400_MAJOR_B_4, FR450_MAJOR_B_4, FR500_MAJOR_B_4, FR550_MAJOR_B_4 } }
},
/* rett$pack $debug */
{
FRV_INSN_RETT, "rett", "rett", 32,
- { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0|A(PRIVILEGED)|A(UNCOND_CTI), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* rei$pack $eir */
{
FRV_INSN_REI, "rei", "rei", 32,
- { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_1, FR550_MAJOR_NONE } }
+ { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_1, FR550_MAJOR_NONE } }
},
/* tra$pack $GRi,$GRj */
{
FRV_INSN_TRA, "tra", "tra", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tno$pack */
{
FRV_INSN_TNO, "tno", "tno", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* teq$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TEQ, "teq", "teq", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tne$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TNE, "tne", "tne", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tle$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TLE, "tle", "tle", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tgt$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TGT, "tgt", "tgt", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tlt$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TLT, "tlt", "tlt", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tge$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TGE, "tge", "tge", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tls$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TLS, "tls", "tls", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* thi$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_THI, "thi", "thi", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tc$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TC, "tc", "tc", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tnc$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TNC, "tnc", "tnc", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tn$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TN, "tn", "tn", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tp$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TP, "tp", "tp", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tv$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TV, "tv", "tv", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tnv$pack $ICCi_2,$GRi,$GRj */
{
FRV_INSN_TNV, "tnv", "tnv", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftra$pack $GRi,$GRj */
{
FRV_INSN_FTRA, "ftra", "ftra", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftno$pack */
{
FRV_INSN_FTNO, "ftno", "ftno", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftne$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTNE, "ftne", "ftne", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* fteq$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTEQ, "fteq", "fteq", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftlg$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTLG, "ftlg", "ftlg", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftue$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTUE, "ftue", "ftue", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftul$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTUL, "ftul", "ftul", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftge$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTGE, "ftge", "ftge", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftlt$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTLT, "ftlt", "ftlt", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftuge$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTUGE, "ftuge", "ftuge", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftug$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTUG, "ftug", "ftug", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftle$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTLE, "ftle", "ftle", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftgt$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTGT, "ftgt", "ftgt", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftule$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTULE, "ftule", "ftule", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftu$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTU, "ftu", "ftu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* fto$pack $FCCi_2,$GRi,$GRj */
{
FRV_INSN_FTO, "fto", "fto", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tira$pack $GRi,$s12 */
{
FRV_INSN_TIRA, "tira", "tira", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tino$pack */
{
FRV_INSN_TINO, "tino", "tino", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tieq$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TIEQ, "tieq", "tieq", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tine$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TINE, "tine", "tine", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tile$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TILE, "tile", "tile", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tigt$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TIGT, "tigt", "tigt", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tilt$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TILT, "tilt", "tilt", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tige$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TIGE, "tige", "tige", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tils$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TILS, "tils", "tils", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tihi$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TIHI, "tihi", "tihi", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tic$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TIC, "tic", "tic", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tinc$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TINC, "tinc", "tinc", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tin$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TIN, "tin", "tin", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tip$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TIP, "tip", "tip", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tiv$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TIV, "tiv", "tiv", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* tinv$pack $ICCi_2,$GRi,$s12 */
{
FRV_INSN_TINV, "tinv", "tinv", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftira$pack $GRi,$s12 */
{
FRV_INSN_FTIRA, "ftira", "ftira", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftino$pack */
{
FRV_INSN_FTINO, "ftino", "ftino", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftine$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTINE, "ftine", "ftine", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftieq$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIEQ, "ftieq", "ftieq", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftilg$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTILG, "ftilg", "ftilg", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftiue$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIUE, "ftiue", "ftiue", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftiul$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIUL, "ftiul", "ftiul", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftige$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIGE, "ftige", "ftige", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftilt$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTILT, "ftilt", "ftilt", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftiuge$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIUGE, "ftiuge", "ftiuge", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftiug$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIUG, "ftiug", "ftiug", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftile$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTILE, "ftile", "ftile", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftigt$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIGT, "ftigt", "ftigt", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftiule$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIULE, "ftiule", "ftiule", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftiu$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIU, "ftiu", "ftiu", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* ftio$pack $FCCi_2,$GRi,$s12 */
{
FRV_INSN_FTIO, "ftio", "ftio", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* break$pack */
{
FRV_INSN_BREAK, "break", "break", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* mtrap$pack */
{
FRV_INSN_MTRAP, "mtrap", "mtrap", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_1, FR450_MAJOR_C_1, FR500_MAJOR_C_1, FR550_MAJOR_C_1 } }
},
/* andcr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_ANDCR, "andcr", "andcr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* orcr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_ORCR, "orcr", "orcr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* xorcr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_XORCR, "xorcr", "xorcr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* nandcr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_NANDCR, "nandcr", "nandcr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* norcr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_NORCR, "norcr", "norcr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* andncr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_ANDNCR, "andncr", "andncr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* orncr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_ORNCR, "orncr", "orncr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* nandncr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_NANDNCR, "nandncr", "nandncr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* norncr$pack $CRi,$CRj,$CRk */
{
FRV_INSN_NORNCR, "norncr", "norncr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* notcr$pack $CRj,$CRk */
{
FRV_INSN_NOTCR, "notcr", "notcr", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_6, FR450_MAJOR_B_6, FR500_MAJOR_B_6, FR550_MAJOR_B_6 } }
},
/* ckra$pack $CRj_int */
{
FRV_INSN_CKRA, "ckra", "ckra", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckno$pack $CRj_int */
{
FRV_INSN_CKNO, "ckno", "ckno", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckeq$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKEQ, "ckeq", "ckeq", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckne$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKNE, "ckne", "ckne", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckle$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKLE, "ckle", "ckle", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckgt$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKGT, "ckgt", "ckgt", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cklt$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKLT, "cklt", "cklt", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckge$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKGE, "ckge", "ckge", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckls$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKLS, "ckls", "ckls", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckhi$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKHI, "ckhi", "ckhi", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckc$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKC, "ckc", "ckc", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cknc$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKNC, "cknc", "cknc", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckn$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKN, "ckn", "ckn", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckp$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKP, "ckp", "ckp", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ckv$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKV, "ckv", "ckv", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cknv$pack $ICCi_3,$CRj_int */
{
FRV_INSN_CKNV, "cknv", "cknv", 32,
- { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0, { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckra$pack $CRj_float */
{
FRV_INSN_FCKRA, "fckra", "fckra", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckno$pack $CRj_float */
{
FRV_INSN_FCKNO, "fckno", "fckno", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckne$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKNE, "fckne", "fckne", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckeq$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKEQ, "fckeq", "fckeq", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fcklg$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKLG, "fcklg", "fcklg", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckue$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKUE, "fckue", "fckue", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckul$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKUL, "fckul", "fckul", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckge$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKGE, "fckge", "fckge", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fcklt$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKLT, "fcklt", "fcklt", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckuge$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKUGE, "fckuge", "fckuge", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckug$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKUG, "fckug", "fckug", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckle$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKLE, "fckle", "fckle", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckgt$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKGT, "fckgt", "fckgt", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fckule$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKULE, "fckule", "fckule", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fcku$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKU, "fcku", "fcku", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* fcko$pack $FCCi_3,$CRj_float */
{
FRV_INSN_FCKO, "fcko", "fcko", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckra$pack $CRj_int,$CCi,$cond */
{
FRV_INSN_CCKRA, "cckra", "cckra", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckno$pack $CRj_int,$CCi,$cond */
{
FRV_INSN_CCKNO, "cckno", "cckno", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckeq$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKEQ, "cckeq", "cckeq", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckne$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKNE, "cckne", "cckne", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckle$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKLE, "cckle", "cckle", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckgt$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKGT, "cckgt", "cckgt", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ccklt$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKLT, "ccklt", "ccklt", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckge$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKGE, "cckge", "cckge", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckls$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKLS, "cckls", "cckls", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckhi$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKHI, "cckhi", "cckhi", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckc$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKC, "cckc", "cckc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ccknc$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKNC, "ccknc", "ccknc", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckn$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKN, "cckn", "cckn", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckp$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKP, "cckp", "cckp", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cckv$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKV, "cckv", "cckv", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* ccknv$pack $ICCi_3,$CRj_int,$CCi,$cond */
{
FRV_INSN_CCKNV, "ccknv", "ccknv", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckra$pack $CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKRA, "cfckra", "cfckra", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckno$pack $CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKNO, "cfckno", "cfckno", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckne$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKNE, "cfckne", "cfckne", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckeq$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKEQ, "cfckeq", "cfckeq", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfcklg$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKLG, "cfcklg", "cfcklg", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckue$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKUE, "cfckue", "cfckue", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckul$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKUL, "cfckul", "cfckul", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckge$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKGE, "cfckge", "cfckge", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfcklt$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKLT, "cfcklt", "cfcklt", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckuge$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKUGE, "cfckuge", "cfckuge", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckug$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKUG, "cfckug", "cfckug", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckle$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKLE, "cfckle", "cfckle", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckgt$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKGT, "cfckgt", "cfckgt", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfckule$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKULE, "cfckule", "cfckule", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfcku$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKU, "cfcku", "cfcku", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cfcko$pack $FCCi_3,$CRj_float,$CCi,$cond */
{
FRV_INSN_CFCKO, "cfcko", "cfcko", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_5, FR450_MAJOR_B_5, FR500_MAJOR_B_5, FR550_MAJOR_B_5 } }
},
/* cjmpl$pack @($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CJMPL, "cjmpl", "cjmpl", 32,
- { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+ { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
},
/* ccalll$pack @($GRi,$GRj),$CCi,$cond */
{
FRV_INSN_CCALLL, "ccalll", "ccalll", 32,
- { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
+ { 0|A(CONDITIONAL)|A(COND_CTI), { (1<<MACH_BASE), UNIT_I0, FR400_MAJOR_I_5, FR450_MAJOR_I_5, FR500_MAJOR_I_5, FR550_MAJOR_I_6 } }
},
/* ici$pack @($GRi,$GRj) */
{
FRV_INSN_ICI, "ici", "ici", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* dci$pack @($GRi,$GRj) */
{
FRV_INSN_DCI, "dci", "dci", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* icei$pack @($GRi,$GRj),$ae */
{
FRV_INSN_ICEI, "icei", "icei", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
},
/* dcei$pack @($GRi,$GRj),$ae */
{
FRV_INSN_DCEI, "dcei", "dcei", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
},
/* dcf$pack @($GRi,$GRj) */
{
FRV_INSN_DCF, "dcf", "dcf", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* dcef$pack @($GRi,$GRj),$ae */
{
FRV_INSN_DCEF, "dcef", "dcef", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_C_2 } }
},
/* witlb$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_WITLB, "witlb", "witlb", 32,
- { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+ { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
},
/* wdtlb$pack $GRk,@($GRi,$GRj) */
{
FRV_INSN_WDTLB, "wdtlb", "wdtlb", 32,
- { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+ { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
},
/* itlbi$pack @($GRi,$GRj) */
{
FRV_INSN_ITLBI, "itlbi", "itlbi", 32,
- { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+ { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
},
/* dtlbi$pack @($GRi,$GRj) */
{
FRV_INSN_DTLBI, "dtlbi", "dtlbi", 32,
- { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+ { 0|A(PRIVILEGED), { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
},
/* icpl$pack $GRi,$GRj,$lock */
{
FRV_INSN_ICPL, "icpl", "icpl", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* dcpl$pack $GRi,$GRj,$lock */
{
FRV_INSN_DCPL, "dcpl", "dcpl", 32,
- { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_I_8 } }
+ { 0, { (1<<MACH_BASE), UNIT_DCPL, FR400_MAJOR_C_2, FR450_MAJOR_I_2, FR500_MAJOR_C_2, FR550_MAJOR_I_8 } }
},
/* icul$pack $GRi */
{
FRV_INSN_ICUL, "icul", "icul", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* dcul$pack $GRi */
{
FRV_INSN_DCUL, "dcul", "dcul", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* bar$pack */
{
FRV_INSN_BAR, "bar", "bar", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
},
/* membar$pack */
{
FRV_INSN_MEMBAR, "membar", "membar", 32,
- { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_C, FR400_MAJOR_C_2, FR450_MAJOR_C_2, FR500_MAJOR_C_2, FR550_MAJOR_C_2 } }
+ },
+/* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+ {
+ FRV_INSN_LRAI, "lrai", "lrai", 32,
+ { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ },
+/* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+ {
+ FRV_INSN_LRAD, "lrad", "lrad", 32,
+ { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ },
+/* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
+ {
+ FRV_INSN_TLBPR, "tlbpr", "tlbpr", 32,
+ { 0, { (1<<MACH_FR450), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_C_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
{
FRV_INSN_COP1, "cop1", "cop1", 32,
- { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
},
/* cop2$pack $s6_1,$CPRi,$CPRj,$CPRk */
{
FRV_INSN_COP2, "cop2", "cop2", 32,
- { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_C, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_C_2, FR550_MAJOR_NONE } }
},
/* clrgr$pack $GRk */
{
FRV_INSN_CLRGR, "clrgr", "clrgr", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
},
/* clrfr$pack $FRk */
{
FRV_INSN_CLRFR, "clrfr", "clrfr", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
},
/* clrga$pack */
{
FRV_INSN_CLRGA, "clrga", "clrga", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
},
/* clrfa$pack */
{
FRV_INSN_CLRFA, "clrfa", "clrfa", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
},
/* commitgr$pack $GRk */
{
FRV_INSN_COMMITGR, "commitgr", "commitgr", 32,
- { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+ { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
},
/* commitfr$pack $FRk */
{
FRV_INSN_COMMITFR, "commitfr", "commitfr", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
},
/* commitga$pack */
{
FRV_INSN_COMMITGA, "commitga", "commitga", 32,
- { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+ { 0, { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
},
/* commitfa$pack */
{
FRV_INSN_COMMITFA, "commitfa", "commitfa", 32,
- { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
+ { 0|A(FR_ACCESS), { (1<<MACH_FRV)|(1<<MACH_FR500)|(1<<MACH_FR550), UNIT_I01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_I_6, FR550_MAJOR_I_7 } }
},
/* fitos$pack $FRintj,$FRk */
{
FRV_INSN_FITOS, "fitos", "fitos", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fstoi$pack $FRj,$FRintk */
{
FRV_INSN_FSTOI, "fstoi", "fstoi", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fitod$pack $FRintj,$FRdoublek */
{
FRV_INSN_FITOD, "fitod", "fitod", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* fdtoi$pack $FRdoublej,$FRintk */
{
FRV_INSN_FDTOI, "fdtoi", "fdtoi", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* fditos$pack $FRintj,$FRk */
{
FRV_INSN_FDITOS, "fditos", "fditos", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* fdstoi$pack $FRj,$FRintk */
{
FRV_INSN_FDSTOI, "fdstoi", "fdstoi", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* nfditos$pack $FRintj,$FRk */
{
FRV_INSN_NFDITOS, "nfditos", "nfditos", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* nfdstoi$pack $FRj,$FRintk */
{
FRV_INSN_NFDSTOI, "nfdstoi", "nfdstoi", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* cfitos$pack $FRintj,$FRk,$CCi,$cond */
{
FRV_INSN_CFITOS, "cfitos", "cfitos", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* cfstoi$pack $FRj,$FRintk,$CCi,$cond */
{
FRV_INSN_CFSTOI, "cfstoi", "cfstoi", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* nfitos$pack $FRintj,$FRk */
{
FRV_INSN_NFITOS, "nfitos", "nfitos", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* nfstoi$pack $FRj,$FRintk */
{
FRV_INSN_NFSTOI, "nfstoi", "nfstoi", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fmovs$pack $FRj,$FRk */
{
FRV_INSN_FMOVS, "fmovs", "fmovs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fmovd$pack $FRdoublej,$FRdoublek */
{
FRV_INSN_FMOVD, "fmovd", "fmovd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* fdmovs$pack $FRj,$FRk */
{
FRV_INSN_FDMOVS, "fdmovs", "fdmovs", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* cfmovs$pack $FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFMOVS, "cfmovs", "cfmovs", 32,
- { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0|A(FR_ACCESS)|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fnegs$pack $FRj,$FRk */
{
FRV_INSN_FNEGS, "fnegs", "fnegs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fnegd$pack $FRdoublej,$FRdoublek */
{
FRV_INSN_FNEGD, "fnegd", "fnegd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* fdnegs$pack $FRj,$FRk */
{
FRV_INSN_FDNEGS, "fdnegs", "fdnegs", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* cfnegs$pack $FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFNEGS, "cfnegs", "cfnegs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fabss$pack $FRj,$FRk */
{
FRV_INSN_FABSS, "fabss", "fabss", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fabsd$pack $FRdoublej,$FRdoublek */
{
FRV_INSN_FABSD, "fabsd", "fabsd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* fdabss$pack $FRj,$FRk */
{
FRV_INSN_FDABSS, "fdabss", "fdabss", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_NONE } }
},
/* cfabss$pack $FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFABSS, "cfabss", "cfabss", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_1, FR550_MAJOR_F_2 } }
},
/* fsqrts$pack $FRj,$FRk */
{
FRV_INSN_FSQRTS, "fsqrts", "fsqrts", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
},
/* fdsqrts$pack $FRj,$FRk */
{
FRV_INSN_FDSQRTS, "fdsqrts", "fdsqrts", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
},
/* nfdsqrts$pack $FRj,$FRk */
{
FRV_INSN_NFDSQRTS, "nfdsqrts", "nfdsqrts", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
},
/* fsqrtd$pack $FRdoublej,$FRdoublek */
{
FRV_INSN_FSQRTD, "fsqrtd", "fsqrtd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
},
/* cfsqrts$pack $FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFSQRTS, "cfsqrts", "cfsqrts", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
},
/* nfsqrts$pack $FRj,$FRk */
{
FRV_INSN_NFSQRTS, "nfsqrts", "nfsqrts", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
},
/* fadds$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FADDS, "fadds", "fadds", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
},
/* fsubs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FSUBS, "fsubs", "fsubs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
},
/* fmuls$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FMULS, "fmuls", "fmuls", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
},
/* fdivs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDIVS, "fdivs", "fdivs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
},
/* faddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
{
FRV_INSN_FADDD, "faddd", "faddd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
},
/* fsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
{
FRV_INSN_FSUBD, "fsubd", "fsubd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
},
/* fmuld$pack $FRdoublei,$FRdoublej,$FRdoublek */
{
FRV_INSN_FMULD, "fmuld", "fmuld", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_NONE } }
},
/* fdivd$pack $FRdoublei,$FRdoublej,$FRdoublek */
{
FRV_INSN_FDIVD, "fdivd", "fdivd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_NONE } }
},
/* cfadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFADDS, "cfadds", "cfadds", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
},
/* cfsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFSUBS, "cfsubs", "cfsubs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
},
/* cfmuls$pack $FRi,$FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFMULS, "cfmuls", "cfmuls", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
},
/* cfdivs$pack $FRi,$FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFDIVS, "cfdivs", "cfdivs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
},
/* nfadds$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFADDS, "nfadds", "nfadds", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
},
/* nfsubs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFSUBS, "nfsubs", "nfsubs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
},
/* nfmuls$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFMULS, "nfmuls", "nfmuls", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_3, FR550_MAJOR_F_3 } }
},
/* nfdivs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDIVS, "nfdivs", "nfdivs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_4, FR550_MAJOR_F_3 } }
},
/* fcmps$pack $FRi,$FRj,$FCCi_2 */
{
FRV_INSN_FCMPS, "fcmps", "fcmps", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
},
/* fcmpd$pack $FRdoublei,$FRdoublej,$FCCi_2 */
{
FRV_INSN_FCMPD, "fcmpd", "fcmpd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_NONE } }
},
/* cfcmps$pack $FRi,$FRj,$FCCi_2,$CCi,$cond */
{
FRV_INSN_CFCMPS, "cfcmps", "cfcmps", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_2, FR550_MAJOR_F_2 } }
},
/* fdcmps$pack $FRi,$FRj,$FCCi_2 */
{
FRV_INSN_FDCMPS, "fdcmps", "fdcmps", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
},
/* fmadds$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FMADDS, "fmadds", "fmadds", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* fmsubs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FMSUBS, "fmsubs", "fmsubs", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* fmaddd$pack $FRdoublei,$FRdoublej,$FRdoublek */
{
FRV_INSN_FMADDD, "fmaddd", "fmaddd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* fmsubd$pack $FRdoublei,$FRdoublej,$FRdoublek */
{
FRV_INSN_FMSUBD, "fmsubd", "fmsubd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* fdmadds$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDMADDS, "fdmadds", "fdmadds", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* nfdmadds$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDMADDS, "nfdmadds", "nfdmadds", 32,
- { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* cfmadds$pack $FRi,$FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFMADDS, "cfmadds", "cfmadds", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* cfmsubs$pack $FRi,$FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFMSUBS, "cfmsubs", "cfmsubs", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0|A(CONDITIONAL), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* nfmadds$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFMADDS, "nfmadds", "nfmadds", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* nfmsubs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFMSUBS, "nfmsubs", "nfmsubs", 32,
- { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0|A(NON_EXCEPTING), { (1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* fmas$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FMAS, "fmas", "fmas", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
},
/* fmss$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FMSS, "fmss", "fmss", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
},
/* fdmas$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDMAS, "fdmas", "fdmas", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* fdmss$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDMSS, "fdmss", "fdmss", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* nfdmas$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDMAS, "nfdmas", "nfdmas", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* nfdmss$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDMSS, "nfdmss", "nfdmss", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* cfmas$pack $FRi,$FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFMAS, "cfmas", "cfmas", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
},
/* cfmss$pack $FRi,$FRj,$FRk,$CCi,$cond */
{
FRV_INSN_CFMSS, "cfmss", "cfmss", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
},
/* fmad$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FMAD, "fmad", "fmad", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* fmsd$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FMSD, "fmsd", "fmsd", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_NONE } }
},
/* nfmas$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFMAS, "nfmas", "nfmas", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
},
/* nfmss$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFMSS, "nfmss", "nfmss", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_5, FR550_MAJOR_F_4 } }
},
/* fdadds$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDADDS, "fdadds", "fdadds", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
},
/* fdsubs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDSUBS, "fdsubs", "fdsubs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
},
/* fdmuls$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDMULS, "fdmuls", "fdmuls", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
},
/* fddivs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDDIVS, "fddivs", "fddivs", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
},
/* fdsads$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDSADS, "fdsads", "fdsads", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
},
/* fdmulcs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_FDMULCS, "fdmulcs", "fdmulcs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
},
/* nfdmulcs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDMULCS, "nfdmulcs", "nfdmulcs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
},
/* nfdadds$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDADDS, "nfdadds", "nfdadds", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
},
/* nfdsubs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDSUBS, "nfdsubs", "nfdsubs", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
},
/* nfdmuls$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDMULS, "nfdmuls", "nfdmuls", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_F_4 } }
},
/* nfddivs$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDDIVS, "nfddivs", "nfddivs", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_7, FR550_MAJOR_NONE } }
},
/* nfdsads$pack $FRi,$FRj,$FRk */
{
FRV_INSN_NFDSADS, "nfdsads", "nfdsads", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_F_4 } }
},
/* nfdcmps$pack $FRi,$FRj,$FCCi_2 */
{
FRV_INSN_NFDCMPS, "nfdcmps", "nfdcmps", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_6, FR550_MAJOR_NONE } }
},
/* mhsetlos$pack $u12,$FRklo */
{
FRV_INSN_MHSETLOS, "mhsetlos", "mhsetlos", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
},
/* mhsethis$pack $u12,$FRkhi */
{
FRV_INSN_MHSETHIS, "mhsethis", "mhsethis", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
},
/* mhdsets$pack $u12,$FRintk */
{
FRV_INSN_MHDSETS, "mhdsets", "mhdsets", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
},
/* mhsetloh$pack $s5,$FRklo */
{
FRV_INSN_MHSETLOH, "mhsetloh", "mhsetloh", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
},
/* mhsethih$pack $s5,$FRkhi */
{
FRV_INSN_MHSETHIH, "mhsethih", "mhsethih", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
},
/* mhdseth$pack $s5,$FRintk */
{
FRV_INSN_MHDSETH, "mhdseth", "mhdseth", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_5 } }
},
/* mand$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MAND, "mand", "mand", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mor$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MOR, "mor", "mor", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mxor$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MXOR, "mxor", "mxor", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmand$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMAND, "cmand", "cmand", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMOR, "cmor", "cmor", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmxor$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMXOR, "cmxor", "cmxor", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mnot$pack $FRintj,$FRintk */
{
FRV_INSN_MNOT, "mnot", "mnot", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmnot$pack $FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMNOT, "cmnot", "cmnot", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mrotli$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MROTLI, "mrotli", "mrotli", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mrotri$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MROTRI, "mrotri", "mrotri", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mwcut$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MWCUT, "mwcut", "mwcut", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mwcuti$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MWCUTI, "mwcuti", "mwcuti", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mcut$pack $ACC40Si,$FRintj,$FRintk */
{
FRV_INSN_MCUT, "mcut", "mcut", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mcuti$pack $ACC40Si,$s6,$FRintk */
{
FRV_INSN_MCUTI, "mcuti", "mcuti", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mcutss$pack $ACC40Si,$FRintj,$FRintk */
{
FRV_INSN_MCUTSS, "mcutss", "mcutss", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mcutssi$pack $ACC40Si,$s6,$FRintk */
{
FRV_INSN_MCUTSSI, "mcutssi", "mcutssi", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mdcutssi$pack $ACC40Si,$s6,$FRintkeven */
{
FRV_INSN_MDCUTSSI, "mdcutssi", "mdcutssi", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDCUTSSI, FR400_MAJOR_M_2, FR450_MAJOR_M_6, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
},
/* maveh$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MAVEH, "maveh", "maveh", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* msllhi$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MSLLHI, "msllhi", "msllhi", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* msrlhi$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MSRLHI, "msrlhi", "msrlhi", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* msrahi$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MSRAHI, "msrahi", "msrahi", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mdrotli$pack $FRintieven,$s6,$FRintkeven */
{
FRV_INSN_MDROTLI, "mdrotli", "mdrotli", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
},
/* mcplhi$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MCPLHI, "mcplhi", "mcplhi", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
},
/* mcpli$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MCPLI, "mcpli", "mcpli", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMLOW, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_3 } }
},
/* msaths$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MSATHS, "msaths", "msaths", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mqsaths$pack $FRintieven,$FRintjeven,$FRintkeven */
{
FRV_INSN_MQSATHS, "mqsaths", "mqsaths", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
},
/* msathu$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MSATHU, "msathu", "msathu", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mcmpsh$pack $FRinti,$FRintj,$FCCk */
{
FRV_INSN_MCMPSH, "mcmpsh", "mcmpsh", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mcmpuh$pack $FRinti,$FRintj,$FCCk */
{
FRV_INSN_MCMPUH, "mcmpuh", "mcmpuh", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mabshs$pack $FRintj,$FRintk */
{
FRV_INSN_MABSHS, "mabshs", "mabshs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_2 } }
},
/* maddhss$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MADDHSS, "maddhss", "maddhss", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* maddhus$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MADDHUS, "maddhus", "maddhus", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* msubhss$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MSUBHSS, "msubhss", "msubhss", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* msubhus$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MSUBHUS, "msubhus", "msubhus", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmaddhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMADDHSS, "cmaddhss", "cmaddhss", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmaddhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMADDHUS, "cmaddhus", "cmaddhus", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmsubhss$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMSUBHSS, "cmsubhss", "cmsubhss", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmsubhus$pack $FRinti,$FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMSUBHUS, "cmsubhus", "cmsubhus", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven */
{
FRV_INSN_MQADDHSS, "mqaddhss", "mqaddhss", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven */
{
FRV_INSN_MQADDHUS, "mqaddhus", "mqaddhus", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven */
{
FRV_INSN_MQSUBHSS, "mqsubhss", "mqsubhss", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* mqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven */
{
FRV_INSN_MQSUBHUS, "mqsubhus", "mqsubhus", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmqaddhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
{
FRV_INSN_CMQADDHSS, "cmqaddhss", "cmqaddhss", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmqaddhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
{
FRV_INSN_CMQADDHUS, "cmqaddhus", "cmqaddhus", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmqsubhss$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
{
FRV_INSN_CMQSUBHSS, "cmqsubhss", "cmqsubhss", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
},
/* cmqsubhus$pack $FRintieven,$FRintjeven,$FRintkeven,$CCi,$cond */
{
FRV_INSN_CMQSUBHUS, "cmqsubhus", "cmqsubhus", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_1, FR550_MAJOR_M_2 } }
+ },
+/* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
+ {
+ FRV_INSN_MQLCLRHS, "mqlclrhs", "mqlclrhs", 32,
+ { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ },
+/* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
+ {
+ FRV_INSN_MQLMTHS, "mqlmths", "mqlmths", 32,
+ { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ },
+/* mqsllhi$pack $FRintieven,$u6,$FRintkeven */
+ {
+ FRV_INSN_MQSLLHI, "mqsllhi", "mqsllhi", 32,
+ { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
+ },
+/* mqsrahi$pack $FRintieven,$u6,$FRintkeven */
+ {
+ FRV_INSN_MQSRAHI, "mqsrahi", "mqsrahi", 32,
+ { 0, { (1<<MACH_FR450), UNIT_FM0, FR400_MAJOR_NONE, FR450_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_NONE } }
},
/* maddaccs$pack $ACC40Si,$ACC40Sk */
{
FRV_INSN_MADDACCS, "maddaccs", "maddaccs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* msubaccs$pack $ACC40Si,$ACC40Sk */
{
FRV_INSN_MSUBACCS, "msubaccs", "msubaccs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* mdaddaccs$pack $ACC40Si,$ACC40Sk */
{
FRV_INSN_MDADDACCS, "mdaddaccs", "mdaddaccs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* mdsubaccs$pack $ACC40Si,$ACC40Sk */
{
FRV_INSN_MDSUBACCS, "mdsubaccs", "mdsubaccs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* masaccs$pack $ACC40Si,$ACC40Sk */
{
FRV_INSN_MASACCS, "masaccs", "masaccs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* mdasaccs$pack $ACC40Si,$ACC40Sk */
{
FRV_INSN_MDASACCS, "mdasaccs", "mdasaccs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_MDUALACC, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* mmulhs$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MMULHS, "mmulhs", "mmulhs", 32,
- { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mmulhu$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MMULHU, "mmulhu", "mmulhu", 32,
- { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mmulxhs$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MMULXHS, "mmulxhs", "mmulxhs", 32,
- { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mmulxhu$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MMULXHU, "mmulxhu", "mmulxhu", 32,
- { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmmulhs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMMULHS, "cmmulhs", "cmmulhs", 32,
- { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmmulhu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMMULHU, "cmmulhu", "cmmulhu", 32,
- { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQMULHS, "mqmulhs", "mqmulhs", 32,
- { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQMULHU, "mqmulhu", "mqmulhu", 32,
- { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqmulxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQMULXHS, "mqmulxhs", "mqmulxhs", 32,
- { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqmulxhu$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQMULXHU, "mqmulxhu", "mqmulxhu", 32,
- { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmqmulhs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMQMULHS, "cmqmulhs", "cmqmulhs", 32,
- { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmqmulhu$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMQMULHU, "cmqmulhu", "cmqmulhu", 32,
- { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL)|A(PRESERVE_OVF), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mmachs$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MMACHS, "mmachs", "mmachs", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mmachu$pack $FRinti,$FRintj,$ACC40Uk */
{
FRV_INSN_MMACHU, "mmachu", "mmachu", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mmrdhs$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MMRDHS, "mmrdhs", "mmrdhs", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mmrdhu$pack $FRinti,$FRintj,$ACC40Uk */
{
FRV_INSN_MMRDHU, "mmrdhu", "mmrdhu", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmmachs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMMACHS, "cmmachs", "cmmachs", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmmachu$pack $FRinti,$FRintj,$ACC40Uk,$CCi,$cond */
{
FRV_INSN_CMMACHU, "cmmachu", "cmmachu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQMACHS, "mqmachs", "mqmachs", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk */
{
FRV_INSN_MQMACHU, "mqmachu", "mqmachu", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmqmachs$pack $FRintieven,$FRintjeven,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMQMACHS, "cmqmachs", "cmqmachs", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmqmachu$pack $FRintieven,$FRintjeven,$ACC40Uk,$CCi,$cond */
{
FRV_INSN_CMQMACHU, "cmqmachu", "cmqmachu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqxmachs$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQXMACHS, "mqxmachs", "mqxmachs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* mqxmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQXMACXHS, "mqxmacxhs", "mqxmacxhs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* mqmacxhs$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQMACXHS, "mqmacxhs", "mqmacxhs", 32,
- { 0, { (1<<MACH_FR400)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_FR400)|(1<<MACH_FR450)|(1<<MACH_FR550), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_NONE, FR550_MAJOR_M_4 } }
},
/* mcpxrs$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MCPXRS, "mcpxrs", "mcpxrs", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mcpxru$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MCPXRU, "mcpxru", "mcpxru", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mcpxis$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MCPXIS, "mcpxis", "mcpxis", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mcpxiu$pack $FRinti,$FRintj,$ACC40Sk */
{
FRV_INSN_MCPXIU, "mcpxiu", "mcpxiu", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmcpxrs$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMCPXRS, "cmcpxrs", "cmcpxrs", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmcpxru$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMCPXRU, "cmcpxru", "cmcpxru", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmcpxis$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMCPXIS, "cmcpxis", "cmcpxis", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* cmcpxiu$pack $FRinti,$FRintj,$ACC40Sk,$CCi,$cond */
{
FRV_INSN_CMCPXIU, "cmcpxiu", "cmcpxiu", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqcpxrs$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQCPXRS, "mqcpxrs", "mqcpxrs", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqcpxru$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQCPXRU, "mqcpxru", "mqcpxru", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqcpxis$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQCPXIS, "mqcpxis", "mqcpxis", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mqcpxiu$pack $FRintieven,$FRintjeven,$ACC40Sk */
{
FRV_INSN_MQCPXIU, "mqcpxiu", "mqcpxiu", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_4, FR550_MAJOR_M_4 } }
},
/* mexpdhw$pack $FRinti,$u6,$FRintk */
{
FRV_INSN_MEXPDHW, "mexpdhw", "mexpdhw", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* cmexpdhw$pack $FRinti,$u6,$FRintk,$CCi,$cond */
{
FRV_INSN_CMEXPDHW, "cmexpdhw", "cmexpdhw", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mexpdhd$pack $FRinti,$u6,$FRintkeven */
{
FRV_INSN_MEXPDHD, "mexpdhd", "mexpdhd", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* cmexpdhd$pack $FRinti,$u6,$FRintkeven,$CCi,$cond */
{
FRV_INSN_CMEXPDHD, "cmexpdhd", "cmexpdhd", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mpackh$pack $FRinti,$FRintj,$FRintk */
{
FRV_INSN_MPACKH, "mpackh", "mpackh", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mdpackh$pack $FRintieven,$FRintjeven,$FRintkeven */
{
FRV_INSN_MDPACKH, "mdpackh", "mdpackh", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_5, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_5, FR550_MAJOR_M_3 } }
},
/* munpackh$pack $FRinti,$FRintkeven */
{
FRV_INSN_MUNPACKH, "munpackh", "munpackh", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mdunpackh$pack $FRintieven,$FRintk */
{
FRV_INSN_MDUNPACKH, "mdunpackh", "mdunpackh", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
},
/* mbtoh$pack $FRintj,$FRintkeven */
{
FRV_INSN_MBTOH, "mbtoh", "mbtoh", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* cmbtoh$pack $FRintj,$FRintkeven,$CCi,$cond */
{
FRV_INSN_CMBTOH, "cmbtoh", "cmbtoh", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mhtob$pack $FRintjeven,$FRintk */
{
FRV_INSN_MHTOB, "mhtob", "mhtob", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* cmhtob$pack $FRintjeven,$FRintk,$CCi,$cond */
{
FRV_INSN_CMHTOB, "cmhtob", "cmhtob", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0|A(CONDITIONAL), { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_2, FR450_MAJOR_M_2, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mbtohe$pack $FRintj,$FRintk */
{
FRV_INSN_MBTOHE, "mbtohe", "mbtohe", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
},
/* cmbtohe$pack $FRintj,$FRintk,$CCi,$cond */
{
FRV_INSN_CMBTOHE, "cmbtohe", "cmbtohe", 32,
- { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
+ { 0|A(CONDITIONAL), { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_7, FR550_MAJOR_NONE } }
},
/* mnop$pack */
{
FRV_INSN_MNOP, "mnop", "mnop", 32,
- { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_1 } }
+ { 0, { (1<<MACH_BASE), UNIT_FMALL, FR400_MAJOR_M_1, FR450_MAJOR_M_1, FR500_MAJOR_M_1, FR550_MAJOR_M_1 } }
},
/* mclracc$pack $ACC40Sk,$A0 */
{
FRV_INSN_MCLRACC_0, "mclracc-0", "mclracc", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
},
/* mclracc$pack $ACC40Sk,$A1 */
{
FRV_INSN_MCLRACC_1, "mclracc-1", "mclracc", 32,
- { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR500_MAJOR_M_6, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_MCLRACC_1, FR400_MAJOR_M_2, FR450_MAJOR_M_4, FR500_MAJOR_M_6, FR550_MAJOR_M_3 } }
},
/* mrdacc$pack $ACC40Si,$FRintk */
{
FRV_INSN_MRDACC, "mrdacc", "mrdacc", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mrdaccg$pack $ACCGi,$FRintk */
{
FRV_INSN_MRDACCG, "mrdaccg", "mrdaccg", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_5, FR500_MAJOR_M_2, FR550_MAJOR_M_3 } }
},
/* mwtacc$pack $FRinti,$ACC40Sk */
{
FRV_INSN_MWTACC, "mwtacc", "mwtacc", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
},
/* mwtaccg$pack $FRinti,$ACCGk */
{
FRV_INSN_MWTACCG, "mwtaccg", "mwtaccg", 32,
- { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
+ { 0, { (1<<MACH_BASE), UNIT_FM01, FR400_MAJOR_M_1, FR450_MAJOR_M_3, FR500_MAJOR_M_3, FR550_MAJOR_M_3 } }
},
/* mcop1$pack $FRi,$FRj,$FRk */
{
FRV_INSN_MCOP1, "mcop1", "mcop1", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
},
/* mcop2$pack $FRi,$FRj,$FRk */
{
FRV_INSN_MCOP2, "mcop2", "mcop2", 32,
- { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
+ { 0, { (1<<MACH_FRV), UNIT_FM01, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_M_1, FR550_MAJOR_NONE } }
},
/* fnop$pack */
{
FRV_INSN_FNOP, "fnop", "fnop", 32,
- { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR500_MAJOR_F_8, FR550_MAJOR_F_1 } }
+ { 0, { (1<<MACH_SIMPLE)|(1<<MACH_TOMCAT)|(1<<MACH_FR500)|(1<<MACH_FR550)|(1<<MACH_FRV), UNIT_FMALL, FR400_MAJOR_NONE, FR450_MAJOR_NONE, FR500_MAJOR_F_8, FR550_MAJOR_F_1 } }
},
};
, H_SPR_EIR23 = 663, H_SPR_EIR24 = 664, H_SPR_EIR25 = 665, H_SPR_EIR26 = 666
, H_SPR_EIR27 = 667, H_SPR_EIR28 = 668, H_SPR_EIR29 = 669, H_SPR_EIR30 = 670
, H_SPR_EIR31 = 671, H_SPR_ESFR0 = 672, H_SPR_ESFR1 = 673, H_SPR_SR0 = 768
- , H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_FSR0 = 1024
+ , H_SPR_SR1 = 769, H_SPR_SR2 = 770, H_SPR_SR3 = 771, H_SPR_SCR0 = 832
+ , H_SPR_SCR1 = 833, H_SPR_SCR2 = 834, H_SPR_SCR3 = 835, H_SPR_FSR0 = 1024
, H_SPR_FSR1 = 1025, H_SPR_FSR2 = 1026, H_SPR_FSR3 = 1027, H_SPR_FSR4 = 1028
, H_SPR_FSR5 = 1029, H_SPR_FSR6 = 1030, H_SPR_FSR7 = 1031, H_SPR_FSR8 = 1032
, H_SPR_FSR9 = 1033, H_SPR_FSR10 = 1034, H_SPR_FSR11 = 1035, H_SPR_FSR12 = 1036
, H_SPR_DAMPR55 = 1911, H_SPR_DAMPR56 = 1912, H_SPR_DAMPR57 = 1913, H_SPR_DAMPR58 = 1914
, H_SPR_DAMPR59 = 1915, H_SPR_DAMPR60 = 1916, H_SPR_DAMPR61 = 1917, H_SPR_DAMPR62 = 1918
, H_SPR_DAMPR63 = 1919, H_SPR_AMCR = 1920, H_SPR_STBAR = 1921, H_SPR_MMCR = 1922
- , H_SPR_DCR = 2048, H_SPR_BRR = 2049, H_SPR_NMAR = 2050, H_SPR_IBAR0 = 2052
- , H_SPR_IBAR1 = 2053, H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056
- , H_SPR_DBAR1 = 2057, H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060
- , H_SPR_DBDR01 = 2061, H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064
- , H_SPR_DBDR11 = 2065, H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068
- , H_SPR_DBDR21 = 2069, H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072
- , H_SPR_DBDR31 = 2073, H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076
- , H_SPR_DBMR01 = 2077, H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080
- , H_SPR_DBMR11 = 2081, H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084
- , H_SPR_DBMR21 = 2085, H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088
- , H_SPR_DBMR31 = 2089, H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092
- , H_SPR_CPCR = 2093, H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097
- , H_SPR_CPEMR0 = 2098, H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848
+ , H_SPR_IAMVR1 = 1925, H_SPR_DAMVR1 = 1927, H_SPR_CXNR = 1936, H_SPR_TTBR = 1937
+ , H_SPR_TPLR = 1938, H_SPR_TPPR = 1939, H_SPR_TPXR = 1940, H_SPR_TIMERH = 1952
+ , H_SPR_TIMERL = 1953, H_SPR_TIMERD = 1954, H_SPR_DCR = 2048, H_SPR_BRR = 2049
+ , H_SPR_NMAR = 2050, H_SPR_BTBR = 2051, H_SPR_IBAR0 = 2052, H_SPR_IBAR1 = 2053
+ , H_SPR_IBAR2 = 2054, H_SPR_IBAR3 = 2055, H_SPR_DBAR0 = 2056, H_SPR_DBAR1 = 2057
+ , H_SPR_DBAR2 = 2058, H_SPR_DBAR3 = 2059, H_SPR_DBDR00 = 2060, H_SPR_DBDR01 = 2061
+ , H_SPR_DBDR02 = 2062, H_SPR_DBDR03 = 2063, H_SPR_DBDR10 = 2064, H_SPR_DBDR11 = 2065
+ , H_SPR_DBDR12 = 2066, H_SPR_DBDR13 = 2067, H_SPR_DBDR20 = 2068, H_SPR_DBDR21 = 2069
+ , H_SPR_DBDR22 = 2070, H_SPR_DBDR23 = 2071, H_SPR_DBDR30 = 2072, H_SPR_DBDR31 = 2073
+ , H_SPR_DBDR32 = 2074, H_SPR_DBDR33 = 2075, H_SPR_DBMR00 = 2076, H_SPR_DBMR01 = 2077
+ , H_SPR_DBMR02 = 2078, H_SPR_DBMR03 = 2079, H_SPR_DBMR10 = 2080, H_SPR_DBMR11 = 2081
+ , H_SPR_DBMR12 = 2082, H_SPR_DBMR13 = 2083, H_SPR_DBMR20 = 2084, H_SPR_DBMR21 = 2085
+ , H_SPR_DBMR22 = 2086, H_SPR_DBMR23 = 2087, H_SPR_DBMR30 = 2088, H_SPR_DBMR31 = 2089
+ , H_SPR_DBMR32 = 2090, H_SPR_DBMR33 = 2091, H_SPR_CPCFR = 2092, H_SPR_CPCR = 2093
+ , H_SPR_CPSR = 2094, H_SPR_CPESR0 = 2096, H_SPR_CPESR1 = 2097, H_SPR_CPEMR0 = 2098
+ , H_SPR_CPEMR1 = 2099, H_SPR_IHSR8 = 3848
} SPR_NAMES;
/* Enum declaration for . */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
MACH_BASE, MACH_FRV, MACH_FR550, MACH_FR500
- , MACH_FR400, MACH_TOMCAT, MACH_SIMPLE, MACH_MAX
+ , MACH_FR450, MACH_FR400, MACH_TOMCAT, MACH_SIMPLE
+ , MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
, UNIT_FMALL, UNIT_FMLOW, UNIT_B0, UNIT_B1
, UNIT_B01, UNIT_C, UNIT_MULT_DIV, UNIT_IACC
, UNIT_LOAD, UNIT_STORE, UNIT_SCAN, UNIT_DCPL
- , UNIT_MDUALACC, UNIT_MCLRACC_1, UNIT_NUM_UNITS
+ , UNIT_MDUALACC, UNIT_MDCUTSSI, UNIT_MCLRACC_1, UNIT_NUM_UNITS
} UNIT_ATTR;
/* Enum declaration for fr400 major insn categories. */
, FR400_MAJOR_C_1, FR400_MAJOR_C_2, FR400_MAJOR_M_1, FR400_MAJOR_M_2
} FR400_MAJOR_ATTR;
+/* Enum declaration for fr450 major insn categories. */
+typedef enum fr450_major_attr {
+ FR450_MAJOR_NONE, FR450_MAJOR_I_1, FR450_MAJOR_I_2, FR450_MAJOR_I_3
+ , FR450_MAJOR_I_4, FR450_MAJOR_I_5, FR450_MAJOR_B_1, FR450_MAJOR_B_2
+ , FR450_MAJOR_B_3, FR450_MAJOR_B_4, FR450_MAJOR_B_5, FR450_MAJOR_B_6
+ , FR450_MAJOR_C_1, FR450_MAJOR_C_2, FR450_MAJOR_M_1, FR450_MAJOR_M_2
+ , FR450_MAJOR_M_3, FR450_MAJOR_M_4, FR450_MAJOR_M_5, FR450_MAJOR_M_6
+} FR450_MAJOR_ATTR;
+
/* Enum declaration for fr500 major insn categories. */
typedef enum fr500_major_attr {
FR500_MAJOR_NONE, FR500_MAJOR_I_1, FR500_MAJOR_I_2, FR500_MAJOR_I_3
, FRV_F_CCOND, FRV_F_HINT, FRV_F_LI, FRV_F_LOCK
, FRV_F_DEBUG, FRV_F_A, FRV_F_AE, FRV_F_SPR_H
, FRV_F_SPR_L, FRV_F_SPR, FRV_F_LABEL16, FRV_F_LABELH6
- , FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_ICCI_1_NULL, FRV_F_ICCI_2_NULL
- , FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL, FRV_F_FCCI_3_NULL
- , FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL, FRV_F_GRK_NULL
- , FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL, FRV_F_RD_NULL
- , FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL, FRV_F_LABEL16_NULL
- , FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3, FRV_F_MISC_NULL_4
- , FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7, FRV_F_MISC_NULL_8
- , FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11, FRV_F_LI_OFF
- , FRV_F_LI_ON, FRV_F_MAX
+ , FRV_F_LABELL18, FRV_F_LABEL24, FRV_F_LRAE, FRV_F_LRAD
+ , FRV_F_LRAS, FRV_F_TLBPROPX, FRV_F_TLBPRL, FRV_F_ICCI_1_NULL
+ , FRV_F_ICCI_2_NULL, FRV_F_ICCI_3_NULL, FRV_F_FCCI_1_NULL, FRV_F_FCCI_2_NULL
+ , FRV_F_FCCI_3_NULL, FRV_F_RS_NULL, FRV_F_GRI_NULL, FRV_F_GRJ_NULL
+ , FRV_F_GRK_NULL, FRV_F_FRI_NULL, FRV_F_FRJ_NULL, FRV_F_ACCJ_NULL
+ , FRV_F_RD_NULL, FRV_F_COND_NULL, FRV_F_CCOND_NULL, FRV_F_S12_NULL
+ , FRV_F_LABEL16_NULL, FRV_F_MISC_NULL_1, FRV_F_MISC_NULL_2, FRV_F_MISC_NULL_3
+ , FRV_F_MISC_NULL_4, FRV_F_MISC_NULL_5, FRV_F_MISC_NULL_6, FRV_F_MISC_NULL_7
+ , FRV_F_MISC_NULL_8, FRV_F_MISC_NULL_9, FRV_F_MISC_NULL_10, FRV_F_MISC_NULL_11
+ , FRV_F_LRA_NULL, FRV_F_TLBPR_NULL, FRV_F_LI_OFF, FRV_F_LI_ON
+ , FRV_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) FRV_F_MAX)
, FRV_OPERAND_U6, FRV_OPERAND_S5, FRV_OPERAND_COND, FRV_OPERAND_CCOND
, FRV_OPERAND_HINT, FRV_OPERAND_HINT_TAKEN, FRV_OPERAND_HINT_NOT_TAKEN, FRV_OPERAND_LI
, FRV_OPERAND_LOCK, FRV_OPERAND_DEBUG, FRV_OPERAND_AE, FRV_OPERAND_LABEL16
- , FRV_OPERAND_LABEL24, FRV_OPERAND_A0, FRV_OPERAND_A1, FRV_OPERAND_FRINTIEVEN
- , FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12, FRV_OPERAND_S12
- , FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16, FRV_OPERAND_SLO16
- , FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S, FRV_OPERAND_PSR_PS
- , FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET, FRV_OPERAND_TBR_TBA
- , FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX
+ , FRV_OPERAND_LABEL24, FRV_OPERAND_LRAE, FRV_OPERAND_LRAD, FRV_OPERAND_LRAS
+ , FRV_OPERAND_TLBPROPX, FRV_OPERAND_TLBPRL, FRV_OPERAND_A0, FRV_OPERAND_A1
+ , FRV_OPERAND_FRINTIEVEN, FRV_OPERAND_FRINTJEVEN, FRV_OPERAND_FRINTKEVEN, FRV_OPERAND_D12
+ , FRV_OPERAND_S12, FRV_OPERAND_U12, FRV_OPERAND_SPR, FRV_OPERAND_ULO16
+ , FRV_OPERAND_SLO16, FRV_OPERAND_UHI16, FRV_OPERAND_PSR_ESR, FRV_OPERAND_PSR_S
+ , FRV_OPERAND_PSR_PS, FRV_OPERAND_PSR_ET, FRV_OPERAND_BPSR_BS, FRV_OPERAND_BPSR_BET
+ , FRV_OPERAND_TBR_TBA, FRV_OPERAND_TBR_TT, FRV_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 81
+#define MAX_OPERANDS 86
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_PRIVILEGED, CGEN_INSN_NON_EXCEPTING
- , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_END_BOOLS
- , CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT, CGEN_INSN_FR400_MAJOR
- , CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_CONDITIONAL, CGEN_INSN_FR_ACCESS, CGEN_INSN_PRESERVE_OVF, CGEN_INSN_AUDIO
+ , CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_UNIT
+ , CGEN_INSN_FR400_MAJOR, CGEN_INSN_FR450_MAJOR, CGEN_INSN_FR500_MAJOR, CGEN_INSN_FR550_MAJOR
+ , CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
case FRV_OPERAND_LI :
print_normal (cd, info, fields->f_LI, 0, pc, length);
break;
+ case FRV_OPERAND_LRAD :
+ print_normal (cd, info, fields->f_LRAD, 0, pc, length);
+ break;
+ case FRV_OPERAND_LRAE :
+ print_normal (cd, info, fields->f_LRAE, 0, pc, length);
+ break;
+ case FRV_OPERAND_LRAS :
+ print_normal (cd, info, fields->f_LRAS, 0, pc, length);
+ break;
+ case FRV_OPERAND_TLBPRL :
+ print_normal (cd, info, fields->f_TLBPRL, 0, pc, length);
+ break;
+ case FRV_OPERAND_TLBPROPX :
+ print_normal (cd, info, fields->f_TLBPRopx, 0, pc, length);
+ break;
case FRV_OPERAND_AE :
print_normal (cd, info, fields->f_ae, 0|(1<<CGEN_OPERAND_HASH_PREFIX), pc, length);
break;
case FRV_OPERAND_LI :
errmsg = insert_normal (cd, fields->f_LI, 0, 0, 25, 1, 32, total_length, buffer);
break;
+ case FRV_OPERAND_LRAD :
+ errmsg = insert_normal (cd, fields->f_LRAD, 0, 0, 4, 1, 32, total_length, buffer);
+ break;
+ case FRV_OPERAND_LRAE :
+ errmsg = insert_normal (cd, fields->f_LRAE, 0, 0, 5, 1, 32, total_length, buffer);
+ break;
+ case FRV_OPERAND_LRAS :
+ errmsg = insert_normal (cd, fields->f_LRAS, 0, 0, 3, 1, 32, total_length, buffer);
+ break;
+ case FRV_OPERAND_TLBPRL :
+ errmsg = insert_normal (cd, fields->f_TLBPRL, 0, 0, 25, 1, 32, total_length, buffer);
+ break;
+ case FRV_OPERAND_TLBPROPX :
+ errmsg = insert_normal (cd, fields->f_TLBPRopx, 0, 0, 28, 3, 32, total_length, buffer);
+ break;
case FRV_OPERAND_AE :
errmsg = insert_normal (cd, fields->f_ae, 0, 0, 25, 1, 32, total_length, buffer);
break;
case FRV_OPERAND_LI :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_LI);
break;
+ case FRV_OPERAND_LRAD :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 4, 1, 32, total_length, pc, & fields->f_LRAD);
+ break;
+ case FRV_OPERAND_LRAE :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 5, 1, 32, total_length, pc, & fields->f_LRAE);
+ break;
+ case FRV_OPERAND_LRAS :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 3, 1, 32, total_length, pc, & fields->f_LRAS);
+ break;
+ case FRV_OPERAND_TLBPRL :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_TLBPRL);
+ break;
+ case FRV_OPERAND_TLBPROPX :
+ length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 3, 32, total_length, pc, & fields->f_TLBPRopx);
+ break;
case FRV_OPERAND_AE :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 25, 1, 32, total_length, pc, & fields->f_ae);
break;
case FRV_OPERAND_LI :
value = fields->f_LI;
break;
+ case FRV_OPERAND_LRAD :
+ value = fields->f_LRAD;
+ break;
+ case FRV_OPERAND_LRAE :
+ value = fields->f_LRAE;
+ break;
+ case FRV_OPERAND_LRAS :
+ value = fields->f_LRAS;
+ break;
+ case FRV_OPERAND_TLBPRL :
+ value = fields->f_TLBPRL;
+ break;
+ case FRV_OPERAND_TLBPROPX :
+ value = fields->f_TLBPRopx;
+ break;
case FRV_OPERAND_AE :
value = fields->f_ae;
break;
case FRV_OPERAND_LI :
value = fields->f_LI;
break;
+ case FRV_OPERAND_LRAD :
+ value = fields->f_LRAD;
+ break;
+ case FRV_OPERAND_LRAE :
+ value = fields->f_LRAE;
+ break;
+ case FRV_OPERAND_LRAS :
+ value = fields->f_LRAS;
+ break;
+ case FRV_OPERAND_TLBPRL :
+ value = fields->f_TLBPRL;
+ break;
+ case FRV_OPERAND_TLBPROPX :
+ value = fields->f_TLBPRopx;
+ break;
case FRV_OPERAND_AE :
value = fields->f_ae;
break;
case FRV_OPERAND_LI :
fields->f_LI = value;
break;
+ case FRV_OPERAND_LRAD :
+ fields->f_LRAD = value;
+ break;
+ case FRV_OPERAND_LRAE :
+ fields->f_LRAE = value;
+ break;
+ case FRV_OPERAND_LRAS :
+ fields->f_LRAS = value;
+ break;
+ case FRV_OPERAND_TLBPRL :
+ fields->f_TLBPRL = value;
+ break;
+ case FRV_OPERAND_TLBPROPX :
+ fields->f_TLBPRopx = value;
+ break;
case FRV_OPERAND_AE :
fields->f_ae = value;
break;
case FRV_OPERAND_LI :
fields->f_LI = value;
break;
+ case FRV_OPERAND_LRAD :
+ fields->f_LRAD = value;
+ break;
+ case FRV_OPERAND_LRAE :
+ fields->f_LRAE = value;
+ break;
+ case FRV_OPERAND_LRAS :
+ fields->f_LRAS = value;
+ break;
+ case FRV_OPERAND_TLBPRL :
+ fields->f_TLBPRL = value;
+ break;
+ case FRV_OPERAND_TLBPROPX :
+ fields->f_TLBPRopx = value;
+ break;
case FRV_OPERAND_AE :
fields->f_ae = value;
break;
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr400_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
+static int fr450_check_insn_major_constraints
+ PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr500_check_insn_major_constraints
PARAMS ((FRV_VLIW *, CGEN_ATTR_VALUE_TYPE));
static int fr550_check_insn_major_constraints
if (major >= FR400_MAJOR_B_1 && major <= FR400_MAJOR_B_6)
return 1; /* is a branch */
break;
+ case bfd_mach_fr450:
+ if (major >= FR450_MAJOR_B_1 && major <= FR450_MAJOR_B_6)
+ return 1; /* is a branch */
+ break;
default:
if (major >= FR500_MAJOR_B_1 && major <= FR500_MAJOR_B_6)
return 1; /* is a branch */
switch (mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
return 0; /* No float insns */
default:
if (major >= FR500_MAJOR_F_1 && major <= FR500_MAJOR_F_8)
if (major >= FR400_MAJOR_M_1 && major <= FR400_MAJOR_M_2)
return 1; /* is a media insn */
break;
+ case bfd_mach_fr450:
+ if (major >= FR450_MAJOR_M_1 && major <= FR450_MAJOR_M_6)
+ return 1; /* is a media insn */
+ break;
default:
if (major >= FR500_MAJOR_M_1 && major <= FR500_MAJOR_M_8)
return 1; /* is a media insn */
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
+ if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+ bfd_mach_fr450))
+ return 1;
if (frv_is_branch_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
+ if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+ bfd_mach_fr450))
+ return 1;
if (frv_is_float_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR),
bfd_mach_fr400))
return 1;
+ if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR),
+ bfd_mach_fr450))
+ return 1;
if (frv_is_media_major (CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR500_MAJOR),
bfd_mach_fr500))
return 1;
/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
+/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */
+/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
+};
+
+/* Some insns are assigned specialized implementation units which map to
+ different actual implementation units on different machines. These
+ tables perform that mapping. */
+static CGEN_ATTR_VALUE_TYPE fr450_unit_mapping[] =
+{
+/* unit in insn actual unit */
+/* NIL */ UNIT_NIL,
+/* I0 */ UNIT_I0,
+/* I1 */ UNIT_I1,
+/* I01 */ UNIT_I01,
+/* I2 */ UNIT_NIL, /* no I2 or I3 unit */
+/* I3 */ UNIT_NIL,
+/* IALL */ UNIT_I01, /* only I0 and I1 units */
+/* FM0 */ UNIT_FM0,
+/* FM1 */ UNIT_FM1,
+/* FM01 */ UNIT_FM01,
+/* FM2 */ UNIT_NIL, /* no F2 or M2 units */
+/* FM3 */ UNIT_NIL, /* no F3 or M3 units */
+/* FMALL */ UNIT_FM01,/* Only F0,F1,M0,M1 units */
+/* FMLOW */ UNIT_FM0, /* Only F0,M0 units */
+/* B0 */ UNIT_B0, /* branches only in B0 unit. */
+/* B1 */ UNIT_B0,
+/* B01 */ UNIT_B0,
+/* C */ UNIT_C,
+/* MULT-DIV */ UNIT_I0, /* multiply and divide only in I0 unit. */
+/* IACC */ UNIT_I01, /* iacc multiply in I0 or I1 unit. */
+/* LOAD */ UNIT_I0, /* load only in I0 unit. */
+/* STORE */ UNIT_I0, /* store only in I0 unit. */
+/* SCAN */ UNIT_I0, /* scan only in I0 unit. */
+/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */
+/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
+/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1. */
/* MCLRACC-1*/ UNIT_FM0 /* mclracc,A==1 insn only in FM0 unit. */
};
/* SCAN */ UNIT_I01, /* scan in I0 or I1 unit. */
/* DCPL */ UNIT_C, /* dcpl only in C unit. */
/* MDUALACC */ UNIT_FM0, /* media dual acc insn only in FM0 unit. */
+/* MDCUTSSI */ UNIT_FM0, /* mdcutssi only in FM0 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
/* SCAN */ UNIT_IALL, /* scan in any integer unit. */
/* DCPL */ UNIT_I0, /* dcpl only in I0 unit. */
/* MDUALACC */ UNIT_FMALL,/* media dual acc insn in all media units */
+/* MDCUTSSI */ UNIT_FM01, /* mdcutssi in FM0 or FM1 unit. */
/* MCLRACC-1*/ UNIT_FM01 /* mclracc,A==1 in FM0 or FM1 unit. */
};
vliw->current_vliw = fr400_allowed_vliw;
vliw->unit_mapping = fr400_unit_mapping;
break;
+ case bfd_mach_fr450:
+ vliw->current_vliw = fr400_allowed_vliw;
+ vliw->unit_mapping = fr450_unit_mapping;
+ break;
case bfd_mach_fr550:
vliw->current_vliw = fr550_allowed_vliw;
vliw->unit_mapping = fr550_unit_mapping;
}
static int
+fr450_check_insn_major_constraints (
+ FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE major
+)
+{
+ CGEN_ATTR_VALUE_TYPE other_major;
+
+ /* Our caller guarantees there's at least one other instruction. */
+ other_major = CGEN_INSN_ATTR_VALUE (vliw->insn[0], CGEN_INSN_FR450_MAJOR);
+
+ /* (M4, M5) and (M4, M6) are allowed. */
+ if (other_major == FR450_MAJOR_M_4)
+ if (major == FR450_MAJOR_M_5 || major == FR450_MAJOR_M_6)
+ return 1;
+
+ /* Otherwise, instructions in even-numbered media categories cannot be
+ executed in parallel with other media instructions. */
+ switch (major)
+ {
+ case FR450_MAJOR_M_2:
+ case FR450_MAJOR_M_4:
+ case FR450_MAJOR_M_6:
+ return !(other_major >= FR450_MAJOR_M_1
+ && other_major <= FR450_MAJOR_M_6);
+
+ case FR450_MAJOR_M_1:
+ case FR450_MAJOR_M_3:
+ case FR450_MAJOR_M_5:
+ return !(other_major == FR450_MAJOR_M_2
+ || other_major == FR450_MAJOR_M_4
+ || other_major == FR450_MAJOR_M_6);
+
+ default:
+ return 1;
+ }
+}
+
+static int
find_unit_in_vliw (
FRV_VLIW *vliw, CGEN_ATTR_VALUE_TYPE unit
)
case bfd_mach_fr400:
rc = fr400_check_insn_major_constraints (vliw, major);
break;
+ case bfd_mach_fr450:
+ rc = fr450_check_insn_major_constraints (vliw, major);
+ break;
case bfd_mach_fr550:
rc = fr550_check_insn_major_constraints (vliw, major, insn);
break;
case bfd_mach_fr400:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR400_MAJOR);
break;
+ case bfd_mach_fr450:
+ major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR450_MAJOR);
+ break;
case bfd_mach_fr550:
major = CGEN_INSN_ATTR_VALUE (insn, CGEN_INSN_FR550_MAJOR);
break;
32, 32, 0x7fffffff, { { F (F_PACK) }, { F (F_RD_NULL) }, { F (F_OP) }, { F (F_RS_NULL) }, { F (F_OPE1) }, { F (F_GRJ_NULL) }, { 0 } }
};
+static const CGEN_IFMT ifmt_lrai = {
+ 32, 32, 0x1fc0fc7, { { F (F_PACK) }, { F (F_GRK) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_LRAE) }, { F (F_LRAD) }, { F (F_LRAS) }, { F (F_LRA_NULL) }, { 0 } }
+};
+
+static const CGEN_IFMT ifmt_tlbpr = {
+ 32, 32, 0x61fc0fc0, { { F (F_PACK) }, { F (F_TLBPR_NULL) }, { F (F_TLBPROPX) }, { F (F_TLBPRL) }, { F (F_OP) }, { F (F_GRI) }, { F (F_OPE1) }, { F (F_GRJ) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_cop1 = {
32, 32, 0x1fc0000, { { F (F_PACK) }, { F (F_CPRK) }, { F (F_OP) }, { F (F_CPRI) }, { F (F_S6_1) }, { F (F_CPRJ) }, { 0 } }
};
32, 32, 0x1fc00c0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_CCI) }, { F (F_COND) }, { F (F_OPE4) }, { F (F_FRJ) }, { 0 } }
};
+static const CGEN_IFMT ifmt_mqsllhi = {
+ 32, 32, 0x1fc0fc0, { { F (F_PACK) }, { F (F_FRK) }, { F (F_OP) }, { F (F_FRI) }, { F (F_OPE1) }, { F (F_U6) }, { 0 } }
+};
+
static const CGEN_IFMT ifmt_maddaccs = {
32, 32, 0x1fc0fff, { { F (F_PACK) }, { F (F_ACC40SK) }, { F (F_OP) }, { F (F_ACC40SI) }, { F (F_OPE1) }, { F (F_ACCJ_NULL) }, { 0 } }
};
{ { MNEM, OP (PACK), 0 } },
& ifmt_bar, { 0xc0fc0 }
},
+/* lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } },
+ & ifmt_lrai, { 0xc0800 }
+ },
+/* lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRK), ',', OP (LRAE), ',', OP (LRAD), ',', OP (LRAS), 0 } },
+ & ifmt_lrai, { 0xc0840 }
+ },
+/* tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (PACK), ' ', OP (GRI), ',', OP (GRJ), ',', OP (TLBPROPX), ',', OP (TLBPRL), 0 } },
+ & ifmt_tlbpr, { 0xc0900 }
+ },
/* cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
{
{ 0, 0, 0, 0 },
{ { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), ',', OP (CCI), ',', OP (COND), 0 } },
& ifmt_cmqaddhss, { 0x1cc00c0 }
},
+/* mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+ & ifmt_mqsaths, { 0x1e00400 }
+ },
+/* mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (FRINTJEVEN), ',', OP (FRINTKEVEN), 0 } },
+ & ifmt_mqsaths, { 0x1e00500 }
+ },
+/* mqsllhi$pack $FRintieven,$u6,$FRintkeven */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } },
+ & ifmt_mqsllhi, { 0x1e00440 }
+ },
+/* mqsrahi$pack $FRintieven,$u6,$FRintkeven */
+ {
+ { 0, 0, 0, 0 },
+ { { MNEM, OP (PACK), ' ', OP (FRINTIEVEN), ',', OP (U6), ',', OP (FRINTKEVEN), 0 } },
+ & ifmt_mqsllhi, { 0x1e004c0 }
+ },
/* maddaccs$pack $ACC40Si,$ACC40Sk */
{
{ 0, 0, 0, 0 },
/* nop$pack */
{
-1, "nop", "nop", 32,
- { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+ { 0|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* ret$pack */
{
-1, "ret", "ret", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_B01, FR400_MAJOR_B_3, FR450_MAJOR_B_3, FR500_MAJOR_B_3, FR550_MAJOR_NONE } }
},
/* cmp$pack $GRi,$GRj,$ICCi_1 */
{
-1, "cmp", "cmp", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* cmpi$pack $GRi,$s10,$ICCi_1 */
{
-1, "cmpi", "cmpi", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* ccmp$pack $GRi,$GRj,$CCi,$cond */
{
-1, "ccmp", "ccmp", 32,
- { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+ { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* mov$pack $GRi,$GRk */
{
-1, "mov", "mov", 32,
- { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+ { 0|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
/* cmov$pack $GRi,$GRk,$CCi,$cond */
{
-1, "cmov", "cmov", 32,
- { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
+ { 0|A(CONDITIONAL)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE), UNIT_IALL, FR400_MAJOR_I_1, FR450_MAJOR_I_1, FR500_MAJOR_I_1, FR550_MAJOR_NONE } }
},
};
, FRV_INSN_DCI, FRV_INSN_ICEI, FRV_INSN_DCEI, FRV_INSN_DCF
, FRV_INSN_DCEF, FRV_INSN_WITLB, FRV_INSN_WDTLB, FRV_INSN_ITLBI
, FRV_INSN_DTLBI, FRV_INSN_ICPL, FRV_INSN_DCPL, FRV_INSN_ICUL
- , FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_COP1
- , FRV_INSN_COP2, FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA
- , FRV_INSN_CLRFA, FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA
- , FRV_INSN_COMMITFA, FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD
- , FRV_INSN_FDTOI, FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS
- , FRV_INSN_NFDSTOI, FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS
- , FRV_INSN_NFSTOI, FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS
- , FRV_INSN_CFMOVS, FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS
- , FRV_INSN_CFNEGS, FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS
- , FRV_INSN_CFABSS, FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS
- , FRV_INSN_FSQRTD, FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS
- , FRV_INSN_FSUBS, FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD
- , FRV_INSN_FSUBD, FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS
- , FRV_INSN_CFSUBS, FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS
- , FRV_INSN_NFSUBS, FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS
- , FRV_INSN_FCMPD, FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS
- , FRV_INSN_FMSUBS, FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS
- , FRV_INSN_NFDMADDS, FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS
- , FRV_INSN_NFMSUBS, FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS
- , FRV_INSN_FDMSS, FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS
- , FRV_INSN_CFMSS, FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS
- , FRV_INSN_NFMSS, FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS
- , FRV_INSN_FDDIVS, FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS
- , FRV_INSN_NFDADDS, FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS
- , FRV_INSN_NFDSADS, FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS
- , FRV_INSN_MHDSETS, FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH
- , FRV_INSN_MAND, FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND
- , FRV_INSN_CMOR, FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT
- , FRV_INSN_MROTLI, FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI
- , FRV_INSN_MCUT, FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI
- , FRV_INSN_MDCUTSSI, FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI
- , FRV_INSN_MSRAHI, FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI
- , FRV_INSN_MSATHS, FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH
- , FRV_INSN_MCMPUH, FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS
- , FRV_INSN_MSUBHSS, FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS
- , FRV_INSN_CMSUBHSS, FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS
- , FRV_INSN_MQSUBHSS, FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS
- , FRV_INSN_CMQSUBHSS, FRV_INSN_CMQSUBHUS, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS
- , FRV_INSN_MDADDACCS, FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS
- , FRV_INSN_MMULHS, FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU
- , FRV_INSN_CMMULHS, FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU
- , FRV_INSN_MQMULXHS, FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU
- , FRV_INSN_MMACHS, FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU
- , FRV_INSN_CMMACHS, FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU
- , FRV_INSN_CMQMACHS, FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS
- , FRV_INSN_MQMACXHS, FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS
- , FRV_INSN_MCPXIU, FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS
- , FRV_INSN_CMCPXIU, FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS
- , FRV_INSN_MQCPXIU, FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD
- , FRV_INSN_CMEXPDHD, FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH
- , FRV_INSN_MDUNPACKH, FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB
- , FRV_INSN_CMHTOB, FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP
- , FRV_INSN_MCLRACC_0, FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG
- , FRV_INSN_MWTACC, FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2
- , FRV_INSN_FNOP
+ , FRV_INSN_DCUL, FRV_INSN_BAR, FRV_INSN_MEMBAR, FRV_INSN_LRAI
+ , FRV_INSN_LRAD, FRV_INSN_TLBPR, FRV_INSN_COP1, FRV_INSN_COP2
+ , FRV_INSN_CLRGR, FRV_INSN_CLRFR, FRV_INSN_CLRGA, FRV_INSN_CLRFA
+ , FRV_INSN_COMMITGR, FRV_INSN_COMMITFR, FRV_INSN_COMMITGA, FRV_INSN_COMMITFA
+ , FRV_INSN_FITOS, FRV_INSN_FSTOI, FRV_INSN_FITOD, FRV_INSN_FDTOI
+ , FRV_INSN_FDITOS, FRV_INSN_FDSTOI, FRV_INSN_NFDITOS, FRV_INSN_NFDSTOI
+ , FRV_INSN_CFITOS, FRV_INSN_CFSTOI, FRV_INSN_NFITOS, FRV_INSN_NFSTOI
+ , FRV_INSN_FMOVS, FRV_INSN_FMOVD, FRV_INSN_FDMOVS, FRV_INSN_CFMOVS
+ , FRV_INSN_FNEGS, FRV_INSN_FNEGD, FRV_INSN_FDNEGS, FRV_INSN_CFNEGS
+ , FRV_INSN_FABSS, FRV_INSN_FABSD, FRV_INSN_FDABSS, FRV_INSN_CFABSS
+ , FRV_INSN_FSQRTS, FRV_INSN_FDSQRTS, FRV_INSN_NFDSQRTS, FRV_INSN_FSQRTD
+ , FRV_INSN_CFSQRTS, FRV_INSN_NFSQRTS, FRV_INSN_FADDS, FRV_INSN_FSUBS
+ , FRV_INSN_FMULS, FRV_INSN_FDIVS, FRV_INSN_FADDD, FRV_INSN_FSUBD
+ , FRV_INSN_FMULD, FRV_INSN_FDIVD, FRV_INSN_CFADDS, FRV_INSN_CFSUBS
+ , FRV_INSN_CFMULS, FRV_INSN_CFDIVS, FRV_INSN_NFADDS, FRV_INSN_NFSUBS
+ , FRV_INSN_NFMULS, FRV_INSN_NFDIVS, FRV_INSN_FCMPS, FRV_INSN_FCMPD
+ , FRV_INSN_CFCMPS, FRV_INSN_FDCMPS, FRV_INSN_FMADDS, FRV_INSN_FMSUBS
+ , FRV_INSN_FMADDD, FRV_INSN_FMSUBD, FRV_INSN_FDMADDS, FRV_INSN_NFDMADDS
+ , FRV_INSN_CFMADDS, FRV_INSN_CFMSUBS, FRV_INSN_NFMADDS, FRV_INSN_NFMSUBS
+ , FRV_INSN_FMAS, FRV_INSN_FMSS, FRV_INSN_FDMAS, FRV_INSN_FDMSS
+ , FRV_INSN_NFDMAS, FRV_INSN_NFDMSS, FRV_INSN_CFMAS, FRV_INSN_CFMSS
+ , FRV_INSN_FMAD, FRV_INSN_FMSD, FRV_INSN_NFMAS, FRV_INSN_NFMSS
+ , FRV_INSN_FDADDS, FRV_INSN_FDSUBS, FRV_INSN_FDMULS, FRV_INSN_FDDIVS
+ , FRV_INSN_FDSADS, FRV_INSN_FDMULCS, FRV_INSN_NFDMULCS, FRV_INSN_NFDADDS
+ , FRV_INSN_NFDSUBS, FRV_INSN_NFDMULS, FRV_INSN_NFDDIVS, FRV_INSN_NFDSADS
+ , FRV_INSN_NFDCMPS, FRV_INSN_MHSETLOS, FRV_INSN_MHSETHIS, FRV_INSN_MHDSETS
+ , FRV_INSN_MHSETLOH, FRV_INSN_MHSETHIH, FRV_INSN_MHDSETH, FRV_INSN_MAND
+ , FRV_INSN_MOR, FRV_INSN_MXOR, FRV_INSN_CMAND, FRV_INSN_CMOR
+ , FRV_INSN_CMXOR, FRV_INSN_MNOT, FRV_INSN_CMNOT, FRV_INSN_MROTLI
+ , FRV_INSN_MROTRI, FRV_INSN_MWCUT, FRV_INSN_MWCUTI, FRV_INSN_MCUT
+ , FRV_INSN_MCUTI, FRV_INSN_MCUTSS, FRV_INSN_MCUTSSI, FRV_INSN_MDCUTSSI
+ , FRV_INSN_MAVEH, FRV_INSN_MSLLHI, FRV_INSN_MSRLHI, FRV_INSN_MSRAHI
+ , FRV_INSN_MDROTLI, FRV_INSN_MCPLHI, FRV_INSN_MCPLI, FRV_INSN_MSATHS
+ , FRV_INSN_MQSATHS, FRV_INSN_MSATHU, FRV_INSN_MCMPSH, FRV_INSN_MCMPUH
+ , FRV_INSN_MABSHS, FRV_INSN_MADDHSS, FRV_INSN_MADDHUS, FRV_INSN_MSUBHSS
+ , FRV_INSN_MSUBHUS, FRV_INSN_CMADDHSS, FRV_INSN_CMADDHUS, FRV_INSN_CMSUBHSS
+ , FRV_INSN_CMSUBHUS, FRV_INSN_MQADDHSS, FRV_INSN_MQADDHUS, FRV_INSN_MQSUBHSS
+ , FRV_INSN_MQSUBHUS, FRV_INSN_CMQADDHSS, FRV_INSN_CMQADDHUS, FRV_INSN_CMQSUBHSS
+ , FRV_INSN_CMQSUBHUS, FRV_INSN_MQLCLRHS, FRV_INSN_MQLMTHS, FRV_INSN_MQSLLHI
+ , FRV_INSN_MQSRAHI, FRV_INSN_MADDACCS, FRV_INSN_MSUBACCS, FRV_INSN_MDADDACCS
+ , FRV_INSN_MDSUBACCS, FRV_INSN_MASACCS, FRV_INSN_MDASACCS, FRV_INSN_MMULHS
+ , FRV_INSN_MMULHU, FRV_INSN_MMULXHS, FRV_INSN_MMULXHU, FRV_INSN_CMMULHS
+ , FRV_INSN_CMMULHU, FRV_INSN_MQMULHS, FRV_INSN_MQMULHU, FRV_INSN_MQMULXHS
+ , FRV_INSN_MQMULXHU, FRV_INSN_CMQMULHS, FRV_INSN_CMQMULHU, FRV_INSN_MMACHS
+ , FRV_INSN_MMACHU, FRV_INSN_MMRDHS, FRV_INSN_MMRDHU, FRV_INSN_CMMACHS
+ , FRV_INSN_CMMACHU, FRV_INSN_MQMACHS, FRV_INSN_MQMACHU, FRV_INSN_CMQMACHS
+ , FRV_INSN_CMQMACHU, FRV_INSN_MQXMACHS, FRV_INSN_MQXMACXHS, FRV_INSN_MQMACXHS
+ , FRV_INSN_MCPXRS, FRV_INSN_MCPXRU, FRV_INSN_MCPXIS, FRV_INSN_MCPXIU
+ , FRV_INSN_CMCPXRS, FRV_INSN_CMCPXRU, FRV_INSN_CMCPXIS, FRV_INSN_CMCPXIU
+ , FRV_INSN_MQCPXRS, FRV_INSN_MQCPXRU, FRV_INSN_MQCPXIS, FRV_INSN_MQCPXIU
+ , FRV_INSN_MEXPDHW, FRV_INSN_CMEXPDHW, FRV_INSN_MEXPDHD, FRV_INSN_CMEXPDHD
+ , FRV_INSN_MPACKH, FRV_INSN_MDPACKH, FRV_INSN_MUNPACKH, FRV_INSN_MDUNPACKH
+ , FRV_INSN_MBTOH, FRV_INSN_CMBTOH, FRV_INSN_MHTOB, FRV_INSN_CMHTOB
+ , FRV_INSN_MBTOHE, FRV_INSN_CMBTOHE, FRV_INSN_MNOP, FRV_INSN_MCLRACC_0
+ , FRV_INSN_MCLRACC_1, FRV_INSN_MRDACC, FRV_INSN_MRDACCG, FRV_INSN_MWTACC
+ , FRV_INSN_MWTACCG, FRV_INSN_MCOP1, FRV_INSN_MCOP2, FRV_INSN_FNOP
} CGEN_INSN_TYPE;
/* Index of `invalid' insn place holder. */
long f_labelH6;
long f_labelL18;
long f_label24;
+ long f_LRAE;
+ long f_LRAD;
+ long f_LRAS;
+ long f_TLBPRopx;
+ long f_TLBPRL;
long f_ICCi_1_null;
long f_ICCi_2_null;
long f_ICCi_3_null;
long f_misc_null_9;
long f_misc_null_10;
long f_misc_null_11;
+ long f_LRA_null;
+ long f_TLBPR_null;
long f_LI_off;
long f_LI_on;
};
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+ * Makefile.in (SIM_OBJS): Add profile-fr450.o.
+ (profile-fr450.o): New dependency.
+ (stamp-cpu): Add fr450 to the list of machs.
+ * sim-frv.h (SPR_IS_ACC): New macro.
+ (H_SPR_ACC4, H_SPR_ACC63, H_SPR_ACCG4, H_SPR_ACCG63): Delete.
+ * cache.c (frv_cache_init, non_cache_access): Handle bfd_mach_fr450.
+ * frv.c (check_register_alignment, check_fr_register_alignment)
+ (check_memory_alignment, do_media_average): Likewise.
+ (frvbf_clear_accumulators): Likewise. Use a mask of valid registers
+ rather than a consecutive range.
+ * interrupts.c (frv_queue_illegal_instruction_interrupt)
+ (frv_queue_non_implemented_instruction_interrupt): Handle
+ bfd_mach_fr450.
+ * memory.c (check_data_read_address, check_readwrite_address)
+ (check_insn_read_address, check_write_address): Likewise.
+ * mloop.in (@cpu@_simulate_insn_prefetch): Likewise.
+ * profile.c (reset_gr_flags, reset_fr_flags, reset_acc_flags)
+ (frvbf_model_insn_before, frvbf_model_insn_after): Likewise.
+ * profile-fr450.c: New file.
+ * registers.c (fr450_spr): New array.
+ (frv_register_control_init): Check its size. Use it for fr450.
+ (frv_check_register_access): Handle bfd_mach_fr450.
+ (frv_check_spr_read_access): Likewise. Generalize accumulator check.
+ * traps.c (frv_core_signal, frvbf_media_cr_not_aligned): Likewise.
+ (frvbf_media_acc_not_aligned): Likewise.
+ (frvbf_media_register_not_aligned): Likewise.
+ * arch.c: Regenerate.
+ * arch.h: Regenerate.
+ * cpu.h: Regenerate.
+ * cpuall.h: Regenerate.
+ * decode.h: Regenerate.
+ * model.c: Regenerate.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
* cache.c (frv_cache_init): Change fr400 cache statistics to match
the fr405.
(non_cache_access): Add missing breaks.
sim-if.o arch.o \
$(FRV_OBJS) \
traps.o interrupts.o memory.o cache.o pipeline.o \
- profile.o profile-fr400.o profile-fr500.o profile-fr550.o options.o \
+ profile.o profile-fr400.o profile-fr450.o profile-fr500.o profile-fr550.o options.o \
devices.o reset.o registers.o \
$(CONFIG_DEVICES)
registers.o: registers.c $(FRVBF_INCLUDE_DEPS)
profile.o: profile.c profile-fr400.h profile-fr500.h profile-fr550.h $(FRVBF_INCLUDE_DEPS)
profile-fr400.o: profile-fr400.c profile-fr400.h $(FRVBF_INCLUDE_DEPS)
+profile-fr450.o: profile-fr450.c $(FRVBF_INCLUDE_DEPS)
profile-fr500.o: profile-fr500.c profile-fr500.h $(FRVBF_INCLUDE_DEPS)
profile-fr550.o: profile-fr550.c profile-fr550.h $(FRVBF_INCLUDE_DEPS)
sim-if.o: sim-if.c $(FRVBF_INCLUDE_DEPS) $(srcdir)/../common/sim-core.h eng.h
stamp-cpu: $(CGEN_READ_SCM) $(CGEN_CPU_SCM) $(CGEN_DECODE_SCM) $(srcdir)/../../cpu/frv.cpu
$(MAKE) cgen-cpu-decode $(CGEN_FLAGS_TO_PASS) \
- cpu=frvbf mach=frv,fr550,fr500,fr400,tomcat,simple SUFFIX= \
+ cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple SUFFIX= \
archfile=$(srcdir)/../../cpu/frv.cpu \
FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" \
EXTRAFILES="$(CGEN_CPU_SEM)"
& fr400_mach,
#endif
#ifdef HAVE_CPU_FRVBF
+ & fr450_mach,
+#endif
+#ifdef HAVE_CPU_FRVBF
& simple_mach,
#endif
0
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_FRV, MODEL_FR550, MODEL_FR500, MODEL_TOMCAT
- , MODEL_FR400, MODEL_SIMPLE, MODEL_MAX
+ , MODEL_FR400, MODEL_FR450, MODEL_SIMPLE, MODEL_MAX
} MODEL_TYPE;
#define MAX_MODELS ((int) MODEL_MAX)
, UNIT_FR400_U_SWAP, UNIT_FR400_U_FR_STORE, UNIT_FR400_U_FR_LOAD, UNIT_FR400_U_GR_STORE
, UNIT_FR400_U_GR_LOAD, UNIT_FR400_U_SET_HILO, UNIT_FR400_U_CHECK, UNIT_FR400_U_TRAP
, UNIT_FR400_U_BRANCH, UNIT_FR400_U_IDIV, UNIT_FR400_U_IMUL, UNIT_FR400_U_INTEGER
- , UNIT_FR400_U_EXEC, UNIT_SIMPLE_U_EXEC, UNIT_MAX
+ , UNIT_FR400_U_EXEC, UNIT_FR450_U_DCUL, UNIT_FR450_U_ICUL, UNIT_FR450_U_DCPL
+ , UNIT_FR450_U_ICPL, UNIT_FR450_U_DCF, UNIT_FR450_U_DCI, UNIT_FR450_U_ICI
+ , UNIT_FR450_U_MEMBAR, UNIT_FR450_U_BARRIER, UNIT_FR450_U_MEDIA_DUAL_HTOB, UNIT_FR450_U_MEDIA_DUAL_EXPAND
+ , UNIT_FR450_U_MEDIA_7, UNIT_FR450_U_MEDIA_6, UNIT_FR450_U_MEDIA_4_MCLRACCA, UNIT_FR450_U_MEDIA_4_ACC_DUAL
+ , UNIT_FR450_U_MEDIA_4_ACCG, UNIT_FR450_U_MEDIA_4, UNIT_FR450_U_MEDIA_3_QUAD, UNIT_FR450_U_MEDIA_3_DUAL
+ , UNIT_FR450_U_MEDIA_3, UNIT_FR450_U_MEDIA_2_ADD_SUB_DUAL, UNIT_FR450_U_MEDIA_2_ADD_SUB, UNIT_FR450_U_MEDIA_2_ACC_DUAL
+ , UNIT_FR450_U_MEDIA_2_ACC, UNIT_FR450_U_MEDIA_2_QUAD, UNIT_FR450_U_MEDIA_2, UNIT_FR450_U_MEDIA_HILO
+ , UNIT_FR450_U_MEDIA_1_QUAD, UNIT_FR450_U_MEDIA_1, UNIT_FR450_U_GR2SPR, UNIT_FR450_U_GR2FR
+ , UNIT_FR450_U_SPR2GR, UNIT_FR450_U_FR2GR, UNIT_FR450_U_SWAP, UNIT_FR450_U_FR_STORE
+ , UNIT_FR450_U_FR_LOAD, UNIT_FR450_U_GR_STORE, UNIT_FR450_U_GR_LOAD, UNIT_FR450_U_SET_HILO
+ , UNIT_FR450_U_CHECK, UNIT_FR450_U_TRAP, UNIT_FR450_U_BRANCH, UNIT_FR450_U_IDIV
+ , UNIT_FR450_U_IMUL, UNIT_FR450_U_INTEGER, UNIT_FR450_U_EXEC, UNIT_SIMPLE_U_EXEC
+ , UNIT_MAX
} UNIT_TYPE;
#define MAX_UNITS (1)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
if (cache->configured_sets == 0)
cache->configured_sets = 512;
if (cache->configured_ways == 0)
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
if (address >= 0xff000000
|| address >= 0xfe000000 && address <= 0xfeffffff)
return 1; /* non-cache access */
} MODEL_FR400_DATA;
typedef struct {
+ DI prev_fp_load;
+ DI prev_fr_p4;
+ DI prev_fr_p6;
+ DI prev_acc_p2;
+ DI prev_acc_p4;
+ DI cur_fp_load;
+ DI cur_fr_p4;
+ DI cur_fr_p6;
+ DI cur_acc_p2;
+ DI cur_acc_p4;
+} MODEL_FR450_DATA;
+
+typedef struct {
int empty;
} MODEL_SIMPLE_DATA;
} sfmt_cmaddhss;
struct { /* */
UINT f_FRi;
+ UINT f_FRk;
+ UINT f_u6;
+ unsigned char in_FRintieven;
+ unsigned char in_FRintkeven;
+ unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+ unsigned char in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+ unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0;
+ unsigned char in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1;
+ unsigned char out_FRintieven;
+ unsigned char out_FRintkeven;
+ unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+ unsigned char out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+ unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0;
+ unsigned char out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1;
+ } sfmt_mqsllhi;
+ struct { /* */
+ UINT f_FRi;
UINT f_FRj;
UINT f_FRk;
unsigned char in_FRi;
f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
f_GRj_null = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+#define EXTRACT_IFMT_LRAI_VARS \
+ UINT f_pack; \
+ UINT f_GRk; \
+ UINT f_op; \
+ UINT f_GRi; \
+ UINT f_ope1; \
+ UINT f_LRAE; \
+ UINT f_LRAD; \
+ UINT f_LRAS; \
+ UINT f_LRA_null; \
+ unsigned int length;
+#define EXTRACT_IFMT_LRAI_CODE \
+ length = 4; \
+ f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+ f_GRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+ f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+ f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+ f_LRAE = EXTRACT_LSB0_UINT (insn, 32, 5, 1); \
+ f_LRAD = EXTRACT_LSB0_UINT (insn, 32, 4, 1); \
+ f_LRAS = EXTRACT_LSB0_UINT (insn, 32, 3, 1); \
+ f_LRA_null = EXTRACT_LSB0_UINT (insn, 32, 2, 3); \
+
+#define EXTRACT_IFMT_TLBPR_VARS \
+ UINT f_pack; \
+ UINT f_TLBPR_null; \
+ UINT f_TLBPRopx; \
+ UINT f_TLBPRL; \
+ UINT f_op; \
+ UINT f_GRi; \
+ UINT f_ope1; \
+ UINT f_GRj; \
+ unsigned int length;
+#define EXTRACT_IFMT_TLBPR_CODE \
+ length = 4; \
+ f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+ f_TLBPR_null = EXTRACT_LSB0_UINT (insn, 32, 30, 2); \
+ f_TLBPRopx = EXTRACT_LSB0_UINT (insn, 32, 28, 3); \
+ f_TLBPRL = EXTRACT_LSB0_UINT (insn, 32, 25, 1); \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+ f_GRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+ f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+ f_GRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
#define EXTRACT_IFMT_COP1_VARS \
UINT f_pack; \
UINT f_CPRk; \
f_ope4 = EXTRACT_LSB0_UINT (insn, 32, 7, 2); \
f_FRj = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+#define EXTRACT_IFMT_MQSLLHI_VARS \
+ UINT f_pack; \
+ UINT f_FRk; \
+ UINT f_op; \
+ UINT f_FRi; \
+ UINT f_ope1; \
+ UINT f_u6; \
+ unsigned int length;
+#define EXTRACT_IFMT_MQSLLHI_CODE \
+ length = 4; \
+ f_pack = EXTRACT_LSB0_UINT (insn, 32, 31, 1); \
+ f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6); \
+ f_op = EXTRACT_LSB0_UINT (insn, 32, 24, 7); \
+ f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6); \
+ f_ope1 = EXTRACT_LSB0_UINT (insn, 32, 11, 6); \
+ f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6); \
+
#define EXTRACT_IFMT_MADDACCS_VARS \
UINT f_pack; \
UINT f_ACC40Sk; \
extern const MACH fr500_mach;
extern const MACH tomcat_mach;
extern const MACH fr400_mach;
+extern const MACH fr450_mach;
extern const MACH simple_mach;
#ifndef WANT_CPU
{ FRV_INSN_DCUL, FRVBF_INSN_DCUL, FRVBF_SFMT_ICUL },
{ FRV_INSN_BAR, FRVBF_INSN_BAR, FRVBF_SFMT_REI },
{ FRV_INSN_MEMBAR, FRVBF_INSN_MEMBAR, FRVBF_SFMT_REI },
+ { FRV_INSN_LRAI, FRVBF_INSN_LRAI, FRVBF_SFMT_REI },
+ { FRV_INSN_LRAD, FRVBF_INSN_LRAD, FRVBF_SFMT_REI },
+ { FRV_INSN_TLBPR, FRVBF_INSN_TLBPR, FRVBF_SFMT_REI },
{ FRV_INSN_COP1, FRVBF_INSN_COP1, FRVBF_SFMT_REI },
{ FRV_INSN_COP2, FRVBF_INSN_COP2, FRVBF_SFMT_REI },
{ FRV_INSN_CLRGR, FRVBF_INSN_CLRGR, FRVBF_SFMT_CLRGR },
{ FRV_INSN_CMQADDHUS, FRVBF_INSN_CMQADDHUS, FRVBF_SFMT_CMQADDHSS },
{ FRV_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHSS, FRVBF_SFMT_CMQADDHSS },
{ FRV_INSN_CMQSUBHUS, FRVBF_INSN_CMQSUBHUS, FRVBF_SFMT_CMQADDHSS },
+ { FRV_INSN_MQLCLRHS, FRVBF_INSN_MQLCLRHS, FRVBF_SFMT_MQSATHS },
+ { FRV_INSN_MQLMTHS, FRVBF_INSN_MQLMTHS, FRVBF_SFMT_MQSATHS },
+ { FRV_INSN_MQSLLHI, FRVBF_INSN_MQSLLHI, FRVBF_SFMT_MQSLLHI },
+ { FRV_INSN_MQSRAHI, FRVBF_INSN_MQSRAHI, FRVBF_SFMT_MQSLLHI },
{ FRV_INSN_MADDACCS, FRVBF_INSN_MADDACCS, FRVBF_SFMT_MADDACCS },
{ FRV_INSN_MSUBACCS, FRVBF_INSN_MSUBACCS, FRVBF_SFMT_MADDACCS },
{ FRV_INSN_MDADDACCS, FRVBF_INSN_MDADDACCS, FRVBF_SFMT_MDADDACCS },
case 26 : itype = FRVBF_INSN_STFU; goto extract_sfmt_stbfu;
case 27 : itype = FRVBF_INSN_STDFU; goto extract_sfmt_stdfu;
case 28 : itype = FRVBF_INSN_STQFU; goto extract_sfmt_ldqfu;
+ case 32 : itype = FRVBF_INSN_LRAI; goto extract_sfmt_rei;
+ case 33 : itype = FRVBF_INSN_LRAD; goto extract_sfmt_rei;
+ case 36 : itype = FRVBF_INSN_TLBPR; goto extract_sfmt_rei;
case 37 : itype = FRVBF_INSN_STC; goto extract_sfmt_stc;
case 38 : itype = FRVBF_INSN_STDC; goto extract_sfmt_stdc;
case 39 : itype = FRVBF_INSN_STQC; goto extract_sfmt_ldqc;
}
case 120 :
{
- unsigned int val = (((insn >> 7) & (1 << 4)) | ((insn >> 6) & (15 << 0)));
+ unsigned int val = (((insn >> 6) & (63 << 0)));
switch (val)
{
case 0 : itype = FRVBF_INSN_MQXMACHS; goto extract_sfmt_mqmachs;
case 13 : itype = FRVBF_INSN_MCPLI; goto extract_sfmt_mcpli;
case 14 : itype = FRVBF_INSN_MDCUTSSI; goto extract_sfmt_mdcutssi;
case 15 : itype = FRVBF_INSN_MQSATHS; goto extract_sfmt_mqsaths;
- case 16 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos;
- case 17 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh;
- case 18 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis;
- case 19 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih;
- case 20 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets;
- case 21 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth;
+ case 16 : itype = FRVBF_INSN_MQLCLRHS; goto extract_sfmt_mqsaths;
+ case 17 : itype = FRVBF_INSN_MQSLLHI; goto extract_sfmt_mqsllhi;
+ case 19 : itype = FRVBF_INSN_MQSRAHI; goto extract_sfmt_mqsllhi;
+ case 20 : itype = FRVBF_INSN_MQLMTHS; goto extract_sfmt_mqsaths;
+ case 32 : itype = FRVBF_INSN_MHSETLOS; goto extract_sfmt_mhsetlos;
+ case 33 : itype = FRVBF_INSN_MHSETLOH; goto extract_sfmt_mhsetloh;
+ case 34 : itype = FRVBF_INSN_MHSETHIS; goto extract_sfmt_mhsethis;
+ case 35 : itype = FRVBF_INSN_MHSETHIH; goto extract_sfmt_mhsethih;
+ case 36 : itype = FRVBF_INSN_MHDSETS; goto extract_sfmt_mhdsets;
+ case 37 : itype = FRVBF_INSN_MHDSETH; goto extract_sfmt_mhdseth;
default : itype = FRVBF_INSN_X_INVALID; goto extract_sfmt_empty;
}
}
return idesc;
}
+ extract_sfmt_mqsllhi:
+ {
+ const IDESC *idesc = &frvbf_insn_data[itype];
+ CGEN_INSN_INT insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ UINT f_FRk;
+ UINT f_FRi;
+ UINT f_u6;
+
+ f_FRk = EXTRACT_LSB0_UINT (insn, 32, 30, 6);
+ f_FRi = EXTRACT_LSB0_UINT (insn, 32, 17, 6);
+ f_u6 = EXTRACT_LSB0_UINT (insn, 32, 5, 6);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_FRi) = f_FRi;
+ FLD (f_FRk) = f_FRk;
+ FLD (f_u6) = f_u6;
+ TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mqsllhi", "f_FRi 0x%x", 'x', f_FRi, "f_FRk 0x%x", 'x', f_FRk, "f_u6 0x%x", 'x', f_u6, (char *) 0));
+
+#if WITH_PROFILE_MODEL_P
+ /* Record the fields for profiling. */
+ if (PROFILE_MODEL_P (current_cpu))
+ {
+ FLD (in_FRintieven) = f_FRi;
+ FLD (in_FRintkeven) = f_FRk;
+ FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+ FLD (in_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+ FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_0) = ((FLD (f_FRi)) + (0));
+ FLD (in_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintieven_1) = ((FLD (f_FRi)) + (1));
+ FLD (out_FRintieven) = f_FRi;
+ FLD (out_FRintkeven) = f_FRk;
+ FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+ FLD (out_h_fr_hi_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+ FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_0) = ((FLD (f_FRk)) + (0));
+ FLD (out_h_fr_lo_UHI_add__DFLT_index_of__DFLT_FRintkeven_1) = ((FLD (f_FRk)) + (1));
+ }
+#endif
+#undef FLD
+ return idesc;
+ }
+
extract_sfmt_maddaccs:
{
const IDESC *idesc = &frvbf_insn_data[itype];
, FRVBF_INSN_DCF, FRVBF_INSN_DCEF, FRVBF_INSN_WITLB, FRVBF_INSN_WDTLB
, FRVBF_INSN_ITLBI, FRVBF_INSN_DTLBI, FRVBF_INSN_ICPL, FRVBF_INSN_DCPL
, FRVBF_INSN_ICUL, FRVBF_INSN_DCUL, FRVBF_INSN_BAR, FRVBF_INSN_MEMBAR
- , FRVBF_INSN_COP1, FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR
- , FRVBF_INSN_CLRGA, FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR
- , FRVBF_INSN_COMMITGA, FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI
- , FRVBF_INSN_FITOD, FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI
- , FRVBF_INSN_NFDITOS, FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI
- , FRVBF_INSN_NFITOS, FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD
- , FRVBF_INSN_FDMOVS, FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD
- , FRVBF_INSN_FDNEGS, FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD
- , FRVBF_INSN_FDABSS, FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS
- , FRVBF_INSN_NFDSQRTS, FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS
- , FRVBF_INSN_FADDS, FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS
- , FRVBF_INSN_FADDD, FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD
- , FRVBF_INSN_CFADDS, FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS
- , FRVBF_INSN_NFADDS, FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS
- , FRVBF_INSN_FCMPS, FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS
- , FRVBF_INSN_FMADDS, FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD
- , FRVBF_INSN_FDMADDS, FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS
- , FRVBF_INSN_NFMADDS, FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS
- , FRVBF_INSN_FDMAS, FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS
- , FRVBF_INSN_CFMAS, FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD
- , FRVBF_INSN_NFMAS, FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS
- , FRVBF_INSN_FDMULS, FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS
- , FRVBF_INSN_NFDMULCS, FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS
- , FRVBF_INSN_NFDDIVS, FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS
- , FRVBF_INSN_MHSETHIS, FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH
- , FRVBF_INSN_MHDSETH, FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR
- , FRVBF_INSN_CMAND, FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT
- , FRVBF_INSN_CMNOT, FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT
- , FRVBF_INSN_MWCUTI, FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS
- , FRVBF_INSN_MCUTSSI, FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI
- , FRVBF_INSN_MSRLHI, FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI
- , FRVBF_INSN_MCPLI, FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU
- , FRVBF_INSN_MCMPSH, FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS
- , FRVBF_INSN_MADDHUS, FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS
- , FRVBF_INSN_CMADDHUS, FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS
- , FRVBF_INSN_MQADDHUS, FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS
- , FRVBF_INSN_CMQADDHUS, FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MADDACCS
- , FRVBF_INSN_MSUBACCS, FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS
- , FRVBF_INSN_MDASACCS, FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS
- , FRVBF_INSN_MMULXHU, FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS
- , FRVBF_INSN_MQMULHU, FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS
- , FRVBF_INSN_CMQMULHU, FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS
- , FRVBF_INSN_MMRDHU, FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS
- , FRVBF_INSN_MQMACHU, FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS
- , FRVBF_INSN_MQXMACXHS, FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU
- , FRVBF_INSN_MCPXIS, FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU
- , FRVBF_INSN_CMCPXIS, FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU
- , FRVBF_INSN_MQCPXIS, FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW
- , FRVBF_INSN_MEXPDHD, FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH
- , FRVBF_INSN_MUNPACKH, FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH
- , FRVBF_INSN_MHTOB, FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE
- , FRVBF_INSN_MNOP, FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC
- , FRVBF_INSN_MRDACCG, FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1
- , FRVBF_INSN_MCOP2, FRVBF_INSN_FNOP, FRVBF_INSN__MAX
+ , FRVBF_INSN_LRAI, FRVBF_INSN_LRAD, FRVBF_INSN_TLBPR, FRVBF_INSN_COP1
+ , FRVBF_INSN_COP2, FRVBF_INSN_CLRGR, FRVBF_INSN_CLRFR, FRVBF_INSN_CLRGA
+ , FRVBF_INSN_CLRFA, FRVBF_INSN_COMMITGR, FRVBF_INSN_COMMITFR, FRVBF_INSN_COMMITGA
+ , FRVBF_INSN_COMMITFA, FRVBF_INSN_FITOS, FRVBF_INSN_FSTOI, FRVBF_INSN_FITOD
+ , FRVBF_INSN_FDTOI, FRVBF_INSN_FDITOS, FRVBF_INSN_FDSTOI, FRVBF_INSN_NFDITOS
+ , FRVBF_INSN_NFDSTOI, FRVBF_INSN_CFITOS, FRVBF_INSN_CFSTOI, FRVBF_INSN_NFITOS
+ , FRVBF_INSN_NFSTOI, FRVBF_INSN_FMOVS, FRVBF_INSN_FMOVD, FRVBF_INSN_FDMOVS
+ , FRVBF_INSN_CFMOVS, FRVBF_INSN_FNEGS, FRVBF_INSN_FNEGD, FRVBF_INSN_FDNEGS
+ , FRVBF_INSN_CFNEGS, FRVBF_INSN_FABSS, FRVBF_INSN_FABSD, FRVBF_INSN_FDABSS
+ , FRVBF_INSN_CFABSS, FRVBF_INSN_FSQRTS, FRVBF_INSN_FDSQRTS, FRVBF_INSN_NFDSQRTS
+ , FRVBF_INSN_FSQRTD, FRVBF_INSN_CFSQRTS, FRVBF_INSN_NFSQRTS, FRVBF_INSN_FADDS
+ , FRVBF_INSN_FSUBS, FRVBF_INSN_FMULS, FRVBF_INSN_FDIVS, FRVBF_INSN_FADDD
+ , FRVBF_INSN_FSUBD, FRVBF_INSN_FMULD, FRVBF_INSN_FDIVD, FRVBF_INSN_CFADDS
+ , FRVBF_INSN_CFSUBS, FRVBF_INSN_CFMULS, FRVBF_INSN_CFDIVS, FRVBF_INSN_NFADDS
+ , FRVBF_INSN_NFSUBS, FRVBF_INSN_NFMULS, FRVBF_INSN_NFDIVS, FRVBF_INSN_FCMPS
+ , FRVBF_INSN_FCMPD, FRVBF_INSN_CFCMPS, FRVBF_INSN_FDCMPS, FRVBF_INSN_FMADDS
+ , FRVBF_INSN_FMSUBS, FRVBF_INSN_FMADDD, FRVBF_INSN_FMSUBD, FRVBF_INSN_FDMADDS
+ , FRVBF_INSN_NFDMADDS, FRVBF_INSN_CFMADDS, FRVBF_INSN_CFMSUBS, FRVBF_INSN_NFMADDS
+ , FRVBF_INSN_NFMSUBS, FRVBF_INSN_FMAS, FRVBF_INSN_FMSS, FRVBF_INSN_FDMAS
+ , FRVBF_INSN_FDMSS, FRVBF_INSN_NFDMAS, FRVBF_INSN_NFDMSS, FRVBF_INSN_CFMAS
+ , FRVBF_INSN_CFMSS, FRVBF_INSN_FMAD, FRVBF_INSN_FMSD, FRVBF_INSN_NFMAS
+ , FRVBF_INSN_NFMSS, FRVBF_INSN_FDADDS, FRVBF_INSN_FDSUBS, FRVBF_INSN_FDMULS
+ , FRVBF_INSN_FDDIVS, FRVBF_INSN_FDSADS, FRVBF_INSN_FDMULCS, FRVBF_INSN_NFDMULCS
+ , FRVBF_INSN_NFDADDS, FRVBF_INSN_NFDSUBS, FRVBF_INSN_NFDMULS, FRVBF_INSN_NFDDIVS
+ , FRVBF_INSN_NFDSADS, FRVBF_INSN_NFDCMPS, FRVBF_INSN_MHSETLOS, FRVBF_INSN_MHSETHIS
+ , FRVBF_INSN_MHDSETS, FRVBF_INSN_MHSETLOH, FRVBF_INSN_MHSETHIH, FRVBF_INSN_MHDSETH
+ , FRVBF_INSN_MAND, FRVBF_INSN_MOR, FRVBF_INSN_MXOR, FRVBF_INSN_CMAND
+ , FRVBF_INSN_CMOR, FRVBF_INSN_CMXOR, FRVBF_INSN_MNOT, FRVBF_INSN_CMNOT
+ , FRVBF_INSN_MROTLI, FRVBF_INSN_MROTRI, FRVBF_INSN_MWCUT, FRVBF_INSN_MWCUTI
+ , FRVBF_INSN_MCUT, FRVBF_INSN_MCUTI, FRVBF_INSN_MCUTSS, FRVBF_INSN_MCUTSSI
+ , FRVBF_INSN_MDCUTSSI, FRVBF_INSN_MAVEH, FRVBF_INSN_MSLLHI, FRVBF_INSN_MSRLHI
+ , FRVBF_INSN_MSRAHI, FRVBF_INSN_MDROTLI, FRVBF_INSN_MCPLHI, FRVBF_INSN_MCPLI
+ , FRVBF_INSN_MSATHS, FRVBF_INSN_MQSATHS, FRVBF_INSN_MSATHU, FRVBF_INSN_MCMPSH
+ , FRVBF_INSN_MCMPUH, FRVBF_INSN_MABSHS, FRVBF_INSN_MADDHSS, FRVBF_INSN_MADDHUS
+ , FRVBF_INSN_MSUBHSS, FRVBF_INSN_MSUBHUS, FRVBF_INSN_CMADDHSS, FRVBF_INSN_CMADDHUS
+ , FRVBF_INSN_CMSUBHSS, FRVBF_INSN_CMSUBHUS, FRVBF_INSN_MQADDHSS, FRVBF_INSN_MQADDHUS
+ , FRVBF_INSN_MQSUBHSS, FRVBF_INSN_MQSUBHUS, FRVBF_INSN_CMQADDHSS, FRVBF_INSN_CMQADDHUS
+ , FRVBF_INSN_CMQSUBHSS, FRVBF_INSN_CMQSUBHUS, FRVBF_INSN_MQLCLRHS, FRVBF_INSN_MQLMTHS
+ , FRVBF_INSN_MQSLLHI, FRVBF_INSN_MQSRAHI, FRVBF_INSN_MADDACCS, FRVBF_INSN_MSUBACCS
+ , FRVBF_INSN_MDADDACCS, FRVBF_INSN_MDSUBACCS, FRVBF_INSN_MASACCS, FRVBF_INSN_MDASACCS
+ , FRVBF_INSN_MMULHS, FRVBF_INSN_MMULHU, FRVBF_INSN_MMULXHS, FRVBF_INSN_MMULXHU
+ , FRVBF_INSN_CMMULHS, FRVBF_INSN_CMMULHU, FRVBF_INSN_MQMULHS, FRVBF_INSN_MQMULHU
+ , FRVBF_INSN_MQMULXHS, FRVBF_INSN_MQMULXHU, FRVBF_INSN_CMQMULHS, FRVBF_INSN_CMQMULHU
+ , FRVBF_INSN_MMACHS, FRVBF_INSN_MMACHU, FRVBF_INSN_MMRDHS, FRVBF_INSN_MMRDHU
+ , FRVBF_INSN_CMMACHS, FRVBF_INSN_CMMACHU, FRVBF_INSN_MQMACHS, FRVBF_INSN_MQMACHU
+ , FRVBF_INSN_CMQMACHS, FRVBF_INSN_CMQMACHU, FRVBF_INSN_MQXMACHS, FRVBF_INSN_MQXMACXHS
+ , FRVBF_INSN_MQMACXHS, FRVBF_INSN_MCPXRS, FRVBF_INSN_MCPXRU, FRVBF_INSN_MCPXIS
+ , FRVBF_INSN_MCPXIU, FRVBF_INSN_CMCPXRS, FRVBF_INSN_CMCPXRU, FRVBF_INSN_CMCPXIS
+ , FRVBF_INSN_CMCPXIU, FRVBF_INSN_MQCPXRS, FRVBF_INSN_MQCPXRU, FRVBF_INSN_MQCPXIS
+ , FRVBF_INSN_MQCPXIU, FRVBF_INSN_MEXPDHW, FRVBF_INSN_CMEXPDHW, FRVBF_INSN_MEXPDHD
+ , FRVBF_INSN_CMEXPDHD, FRVBF_INSN_MPACKH, FRVBF_INSN_MDPACKH, FRVBF_INSN_MUNPACKH
+ , FRVBF_INSN_MDUNPACKH, FRVBF_INSN_MBTOH, FRVBF_INSN_CMBTOH, FRVBF_INSN_MHTOB
+ , FRVBF_INSN_CMHTOB, FRVBF_INSN_MBTOHE, FRVBF_INSN_CMBTOHE, FRVBF_INSN_MNOP
+ , FRVBF_INSN_MCLRACC_0, FRVBF_INSN_MCLRACC_1, FRVBF_INSN_MRDACC, FRVBF_INSN_MRDACCG
+ , FRVBF_INSN_MWTACC, FRVBF_INSN_MWTACCG, FRVBF_INSN_MCOP1, FRVBF_INSN_MCOP2
+ , FRVBF_INSN_FNOP, FRVBF_INSN__MAX
} FRVBF_INSN_TYPE;
/* Enum declaration for semantic formats in cpu family frvbf. */
, FRVBF_SFMT_MWCUTI, FRVBF_SFMT_MCUT, FRVBF_SFMT_MCUTI, FRVBF_SFMT_MDCUTSSI
, FRVBF_SFMT_MSLLHI, FRVBF_SFMT_MDROTLI, FRVBF_SFMT_MCPLHI, FRVBF_SFMT_MCPLI
, FRVBF_SFMT_MSATHS, FRVBF_SFMT_MQSATHS, FRVBF_SFMT_MCMPSH, FRVBF_SFMT_MABSHS
- , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MADDACCS, FRVBF_SFMT_MDADDACCS
- , FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS, FRVBF_SFMT_CMMULHS
- , FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS, FRVBF_SFMT_MMACHU
- , FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS, FRVBF_SFMT_MQMACHU
- , FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS, FRVBF_SFMT_CMCPXRS
- , FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW, FRVBF_SFMT_MEXPDHD
- , FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH, FRVBF_SFMT_MUNPACKH
- , FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH, FRVBF_SFMT_MHTOB
- , FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE, FRVBF_SFMT_MCLRACC_0
- , FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC, FRVBF_SFMT_MWTACCG
+ , FRVBF_SFMT_CMADDHSS, FRVBF_SFMT_CMQADDHSS, FRVBF_SFMT_MQSLLHI, FRVBF_SFMT_MADDACCS
+ , FRVBF_SFMT_MDADDACCS, FRVBF_SFMT_MASACCS, FRVBF_SFMT_MDASACCS, FRVBF_SFMT_MMULHS
+ , FRVBF_SFMT_CMMULHS, FRVBF_SFMT_MQMULHS, FRVBF_SFMT_CMQMULHS, FRVBF_SFMT_MMACHS
+ , FRVBF_SFMT_MMACHU, FRVBF_SFMT_CMMACHS, FRVBF_SFMT_CMMACHU, FRVBF_SFMT_MQMACHS
+ , FRVBF_SFMT_MQMACHU, FRVBF_SFMT_CMQMACHS, FRVBF_SFMT_CMQMACHU, FRVBF_SFMT_MCPXRS
+ , FRVBF_SFMT_CMCPXRS, FRVBF_SFMT_MQCPXRS, FRVBF_SFMT_MEXPDHW, FRVBF_SFMT_CMEXPDHW
+ , FRVBF_SFMT_MEXPDHD, FRVBF_SFMT_CMEXPDHD, FRVBF_SFMT_MPACKH, FRVBF_SFMT_MDPACKH
+ , FRVBF_SFMT_MUNPACKH, FRVBF_SFMT_MDUNPACKH, FRVBF_SFMT_MBTOH, FRVBF_SFMT_CMBTOH
+ , FRVBF_SFMT_MHTOB, FRVBF_SFMT_CMHTOB, FRVBF_SFMT_MBTOHE, FRVBF_SFMT_CMBTOHE
+ , FRVBF_SFMT_MCLRACC_0, FRVBF_SFMT_MRDACC, FRVBF_SFMT_MRDACCG, FRVBF_SFMT_MWTACC
+ , FRVBF_SFMT_MWTACCG
} FRVBF_SFMT_TYPE;
/* Function unit handlers (user written). */
extern int frvbf_model_fr400_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/);
extern int frvbf_model_fr400_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
extern int frvbf_model_fr400_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr450_u_dcul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_icul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_dcpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_icpl (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_dcf (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_dci (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_ici (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_membar (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr450_u_barrier (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr450_u_media_dual_htob (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_dual_expand (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_7 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FCCk*/);
+extern int frvbf_model_fr450_u_media_6 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
+extern int frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_4_accg (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACCGi*/, INT /*FRinti*/, INT /*ACCGk*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_4 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_3_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_3_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_3 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr450_u_media_2_acc (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ACC40Si*/, INT /*ACC40Sk*/);
+extern int frvbf_model_fr450_u_media_2_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
+extern int frvbf_model_fr450_u_media_2 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*ACC40Sk*/, INT /*ACC40Uk*/);
+extern int frvbf_model_fr450_u_media_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRkhi*/, INT /*FRklo*/);
+extern int frvbf_model_fr450_u_media_1_quad (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_media_1 (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRinti*/, INT /*FRintj*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_gr2spr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*spr*/);
+extern int frvbf_model_fr450_u_gr2fr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRj*/, INT /*FRintk*/);
+extern int frvbf_model_fr450_u_spr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*spr*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_fr2gr (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*FRintk*/, INT /*GRj*/);
+extern int frvbf_model_fr450_u_swap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/);
+extern int frvbf_model_fr450_u_fr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr450_u_fr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*FRintk*/, INT /*FRdoublek*/);
+extern int frvbf_model_fr450_u_gr_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr450_u_gr_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*GRdoublek*/);
+extern int frvbf_model_fr450_u_set_hilo (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRkhi*/, INT /*GRklo*/);
+extern int frvbf_model_fr450_u_check (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*ICCi_3*/, INT /*FCCi_3*/);
+extern int frvbf_model_fr450_u_trap (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr450_u_branch (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*ICCi_2*/, INT /*FCCi_2*/);
+extern int frvbf_model_fr450_u_idiv (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr450_u_imul (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRdoublek*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr450_u_integer (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*GRi*/, INT /*GRj*/, INT /*GRk*/, INT /*ICCi_1*/);
+extern int frvbf_model_fr450_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
extern int frvbf_model_simple_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
/* Profiling before/after handlers (user written) */
#include "sim-options.h"
-/* Not defined in the cgen cpu file for access restriction purposes. */
-#define H_SPR_ACC4 1412
-#define H_SPR_ACC63 1471
-#define H_SPR_ACCG4 1476
-#define H_SPR_ACCG63 1535
+/* True if SPR is the number of accumulator or accumulator guard register. */
+#define SPR_IS_ACC(SPR) ((SPR) >= 1408 && (SPR) <= 1535)
/* Initialization of the frv cpu. */
void frv_initialize (SIM_CPU *, SIM_DESC);
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
+ /* Note: there is a discrepancy between V2.2 of the FR400
+ instruction manual and the various FR4xx LSI specs.
+ The former claims that unaligned registers cause a
+ register_exception while the latter say it's an
+ illegal_instruction. The LSI specs appear to be
+ correct; in fact, the FR4xx series is not documented
+ as having a register_exception. */
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
+ /* See comment in check_register_alignment(). */
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
SIM_DESC sd = CPU_STATE (current_cpu);
switch (STATE_ARCHITECTURE (sd)->mach)
{
+ /* See comment in check_register_alignment(). */
case bfd_mach_fr400:
+ case bfd_mach_fr450:
frv_queue_data_access_error_interrupt (current_cpu, address);
break;
case bfd_mach_frvtomcat:
frvbf_clear_accumulators (SIM_CPU *current_cpu, SI acc_ix, int A)
{
SIM_DESC sd = CPU_STATE (current_cpu);
- int acc_num =
- (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 8 :
- (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 8 :
- (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 4 :
+ int acc_mask =
+ (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500) ? 7 :
+ (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr550) ? 7 :
+ (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450) ? 11 :
+ (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400) ? 3 :
63;
FRV_PROFILE_STATE *ps = CPU_PROFILE_STATE (current_cpu);
{
/* This instruction is a nop if the referenced accumulator is not
implemented. */
- if (acc_ix < acc_num)
+ if ((acc_ix & acc_mask) == acc_ix)
sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, acc_ix, 0);
}
else
{
/* Clear all implemented accumulators. */
int i;
- for (i = 0; i < acc_num; ++i)
- sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0);
+ for (i = 0; i <= acc_mask; ++i)
+ if ((i & acc_mask) == i)
+ sim_queue_fn_di_write (current_cpu, frvbf_h_acc40S_set, i, 0);
}
}
\f
HI result = sum >> 1;
int rounding_value;
- /* On fr400 and fr550, check the rounding mode. On other machines rounding is always
- toward negative infinity and the result is already correctly rounded. */
+ /* On fr4xx and fr550, check the rounding mode. On other machines
+ rounding is always toward negative infinity and the result is
+ already correctly rounded. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
/* Need to check rounding mode. */
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
/* Check whether rounding will be required. Rounding will be required
if the sum is an odd number. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
break;
default:
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
break;
default:
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
address = fr400_check_data_read_address (current_cpu, address,
align_mask);
break;
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
address = fr400_check_readwrite_address (current_cpu, address,
align_mask);
break;
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
address = fr400_check_insn_read_address (current_cpu, address,
align_mask);
break;
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
address = fr400_check_write_address (current_cpu, address, align_mask);
break;
case bfd_mach_frvtomcat:
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
simulate_dual_insn_prefetch (current_cpu, vpc, 8);
break;
case bfd_mach_frvtomcat:
}
static int
+model_frv_lrai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_lrad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_tlbpr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_frv_cop1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
}
static int
+model_frv_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqlmths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqsllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_frv_mqsrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_frv_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_frv_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
}
static int
+model_fr550_lrai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_lrad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_tlbpr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr550_cop1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
}
static int
-model_fr550_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_ACC40Si = -1;
- INT out_ACC40Sk = -1;
- in_ACC40Si = FLD (in_ACC40Si);
- out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
- cycles += frvbf_model_fr550_u_media_4_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr550_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_mqlmths (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_ACC40Si = -1;
- INT out_ACC40Sk = -1;
- in_ACC40Si = FLD (in_ACC40Si);
- out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
- cycles += frvbf_model_fr550_u_media_4_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr550_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_mqsllhi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_ACC40Si = -1;
- INT out_ACC40Sk = -1;
- in_ACC40Si = FLD (in_ACC40Si);
- out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
- cycles += frvbf_model_fr550_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr550_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_mqsrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr550_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
- cycles += frvbf_model_fr550_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr550_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
- cycles += frvbf_model_fr550_u_media_4_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr550_u_media_4_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr550_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
- cycles += frvbf_model_fr550_u_media_4_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr550_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr550_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_cmmachs.f
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- in_FRinti = FLD (in_FRinti);
- in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr550_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_masaccs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_cmmachs.f
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- in_FRinti = FLD (in_FRinti);
- in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr550_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_cmmachs.f
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- in_FRinti = FLD (in_FRinti);
- in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr550_u_media_4_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr550_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr550_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr550_u_media_4 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr550_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
}
static int
+model_fr500_lrai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_lrad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_tlbpr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr500_cop1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
}
static int
+model_fr500_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqlmths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqsllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr500_mqsrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr500_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr500_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
}
static int
+model_tomcat_lrai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_lrad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_tlbpr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_tomcat_cop1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
}
static int
+model_tomcat_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqlmths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqsllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_tomcat_mqsrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_tomcat_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_tomcat_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
}
static int
+model_fr400_lrai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_lrad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_tlbpr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_fr400_cop1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
}
static int
-model_fr400_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_ACC40Si = -1;
- INT out_ACC40Sk = -1;
- in_ACC40Si = FLD (in_ACC40Si);
- out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
- cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mqlmths (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_ACC40Si = -1;
- INT out_ACC40Sk = -1;
- in_ACC40Si = FLD (in_ACC40Si);
- out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
- cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mqsllhi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_ACC40Si = -1;
- INT out_ACC40Sk = -1;
- in_ACC40Si = FLD (in_ACC40Si);
- out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
- cycles += frvbf_model_fr400_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mqsrahi (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_ACC40Si = -1;
- INT out_ACC40Sk = -1;
- in_ACC40Si = FLD (in_ACC40Si);
- out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
- cycles += frvbf_model_fr400_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
- cycles += frvbf_model_fr400_u_media_2_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
- cycles += frvbf_model_fr400_u_media_2_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_cmmachs.f
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- in_FRinti = FLD (in_FRinti);
- in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_cmmachs.f
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- in_FRinti = FLD (in_FRinti);
- in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_masaccs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_cmmachs.f
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- in_FRinti = FLD (in_FRinti);
- in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_media_2_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_cmmachs.f
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
+ INT in_ACC40Si = -1;
INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- in_FRinti = FLD (in_FRinti);
- in_FRintj = FLD (in_FRintj);
+ in_ACC40Si = FLD (in_ACC40Si);
out_ACC40Sk = FLD (out_ACC40Sk);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_media_2_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
}
static int
-model_fr400_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
}
static int
-model_fr400_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cmqmachs.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
- INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- out_ACC40Sk = FLD (out_ACC40Sk);
- in_FRinti = FLD (in_FRintieven);
- in_FRintj = FLD (in_FRintjeven);
- if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
- }
- return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cmqmachs.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
- INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- out_ACC40Sk = FLD (out_ACC40Sk);
- in_FRinti = FLD (in_FRintieven);
- in_FRintj = FLD (in_FRintjeven);
- if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
- }
- return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cmqmachs.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
- INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- out_ACC40Sk = FLD (out_ACC40Sk);
- in_FRinti = FLD (in_FRintieven);
- in_FRintj = FLD (in_FRintjeven);
- if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
- }
- return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cmqmachs.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
- INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- out_ACC40Sk = FLD (out_ACC40Sk);
- in_FRinti = FLD (in_FRintieven);
- in_FRintj = FLD (in_FRintjeven);
- if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
- }
- return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cmqmachs.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
- INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- out_ACC40Sk = FLD (out_ACC40Sk);
- in_FRinti = FLD (in_FRintieven);
- in_FRintj = FLD (in_FRintjeven);
- if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
- }
- return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
-{
-#define FLD(f) abuf->fields.sfmt_cmqmachs.f
- const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
- const IDESC * UNUSED idesc = abuf->idesc;
- int cycles = 0;
- {
- int referenced = 0;
- int UNUSED insn_referenced = abuf->written;
- INT in_FRinti = -1;
- INT in_FRintj = -1;
- INT out_ACC40Sk = -1;
- INT out_ACC40Uk = -1;
- out_ACC40Sk = FLD (out_ACC40Sk);
- in_FRinti = FLD (in_FRintieven);
- in_FRintj = FLD (in_FRintjeven);
- if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
- }
- return cycles;
-#undef FLD
-}
-
-static int
-model_fr400_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
out_ACC40Sk = FLD (out_ACC40Sk);
- if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
}
static int
-model_fr400_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
{
-#define FLD(f) abuf->fields.sfmt_cmmachu.f
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
const IDESC * UNUSED idesc = abuf->idesc;
int cycles = 0;
INT out_ACC40Uk = -1;
in_FRinti = FLD (in_FRinti);
in_FRintj = FLD (in_FRintj);
- out_ACC40Uk = FLD (out_ACC40Uk);
- if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
- if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
- if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
}
static int
-model_fr400_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr400_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 19)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 19)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdpackh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr400_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_munpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_munpackh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdunpackh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtoh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ in_FRintj = FLD (in_FRintjeven);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmhtob.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ in_FRintj = FLD (in_FRintjeven);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr400_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmbtohe.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_FRintk = -1;
+ cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_FRintk = -1;
+ cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mrdaccg.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACCGi = -1;
+ INT in_FRinti = -1;
+ INT out_ACCGk = -1;
+ INT out_FRintk = -1;
+ in_ACCGi = FLD (in_ACCGi);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr400_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_FRintk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwtaccg.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACCGi = -1;
+ INT in_FRinti = -1;
+ INT out_ACCGk = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_ACCGk = FLD (out_ACCGk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr400_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr400_fnop (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_add (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_and (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_or (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_xor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_not (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nsdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_udiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_smul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_umul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_smu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_smass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_smsss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smass.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_srl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_slass (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_scutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_scutss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_scan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cadd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csmul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csdiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cudiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csrl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cscan (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_addcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_subcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_andcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_orcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_xorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_srlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_smulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_umulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_caddcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csubcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csmulcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_csmulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_candcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_corcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cxorcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csllcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csrlcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csracc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_caddcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_addx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_subx (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_addxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_subxcc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_addss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_subss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_addi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_subi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_andi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_xori (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nsdivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_udivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_idiv (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nudivi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_smuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_umuli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_slli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_srli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_srai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_scani (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_addicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_subicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_andicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_oricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_xoricc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_smulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_umulicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRdoublek = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_imul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRdoublek, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sllicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_srlicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sraicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_addxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_subxi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_addxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_subxicc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addicc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmpb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmpba (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_ICCi_1 = FLD (out_ICCi_1);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_setlo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlo.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_GRkhi = -1;
+ INT out_GRklo = -1;
+ out_GRklo = FLD (out_GRklo);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sethi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_sethi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_GRkhi = -1;
+ INT out_GRklo = -1;
+ out_GRkhi = FLD (out_GRkhi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_set_hilo (current_cpu, idesc, 0, referenced, out_GRkhi, out_GRklo);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_setlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_ICCi_1 = -1;
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_integer (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nlduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_addcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lddc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nlddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nlduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nlddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lddcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nlddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldsbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldubi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldshi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nlduhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldhfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ldbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ out_FRdoublek = FLD (out_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nlddi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smuli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nlddfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_lddfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nldqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_st (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_std (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRdoublek = FLD (in_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRdoublek = FLD (in_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stdc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_smulcc.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stqf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stqc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRdoublek = FLD (in_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRdoublek = FLD (in_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stdcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stqfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stqcu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdcu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldsb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldub (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clduh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldhf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clddf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldsbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldubu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldshu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clduhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldsbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 8)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldhfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cldbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clddu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ INT out_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRdoublek = FLD (out_GRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 7)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk, out_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clddfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_clddfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ INT out_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_FRdoublek = FLD (out_FRdoublek);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_load (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_FRintk, out_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cldqu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cst (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstbf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csthf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRdoublek = FLD (in_GRdoublek);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstdf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRdoublek = FLD (in_FRdoublek);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csthu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRk = FLD (in_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstbfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_csthfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstbfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRintk = FLD (in_FRintk);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstdu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_GRdoublek = FLD (in_GRdoublek);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cstdfu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cstdfu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FRdoublek = FLD (in_FRdoublek);
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sthi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRk = FLD (in_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stbfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_sthfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stbfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_FRintk = FLD (in_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stdi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_GRk = -1;
+ INT in_GRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRdoublek = FLD (in_GRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_gr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_GRk, in_GRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stdfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_FRintk = -1;
+ INT in_FRdoublek = -1;
+ in_GRi = FLD (in_GRi);
+ in_FRdoublek = FLD (in_FRdoublek);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_fr_store (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_FRintk, in_FRdoublek);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stqi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_stqfi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_stdfi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_swap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_swapi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ in_GRi = FLD (in_GRi);
+ out_GRk = FLD (out_GRk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cswap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cswap.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT out_GRk = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ out_GRk = FLD (out_GRk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_swap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, out_GRk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_movgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_movfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintk = -1;
+ INT out_GRj = -1;
+ in_FRintk = FLD (in_FRintk);
+ out_GRj = FLD (out_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_movgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_movfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintk = -1;
+ INT out_GRj = -1;
+ in_FRintk = FLD (in_FRintk);
+ out_GRj = FLD (out_GRj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_movgfq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgfq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_movfgq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movfgq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmovgf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmovfg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintk = -1;
+ INT out_GRj = -1;
+ in_FRintk = FLD (in_FRintk);
+ out_GRj = FLD (out_GRj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmovgfd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovgfd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_FRintk = -1;
+ in_GRj = FLD (in_GRj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_gr2fr (current_cpu, idesc, 0, referenced, in_GRj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmovfgd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmovfgd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRintk = -1;
+ INT out_GRj = -1;
+ in_FRintk = FLD (in_FRintk);
+ out_GRj = FLD (out_GRj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_fr2gr (current_cpu, idesc, 0, referenced, in_FRintk, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_movgs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movgs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRj = -1;
+ INT out_spr = -1;
+ in_GRj = FLD (in_GRj);
+ out_spr = FLD (out_spr);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_gr2spr (current_cpu, idesc, 0, referenced, in_GRj, out_spr);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_movsg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_movsg.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_spr = -1;
+ INT out_GRj = -1;
+ in_spr = FLD (in_spr);
+ out_GRj = FLD (out_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_spr2gr (current_cpu, idesc, 0, referenced, in_spr, out_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_beq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_blt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_beq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fblg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fblt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fble (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbo (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fbne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bctrlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_beqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_blelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_blslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bhilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bceqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bclelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bclslr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bchilr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcnclr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcnlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcplr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bcnvlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_bceqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_ICCi_2 = FLD (in_ICCi_2);
+ referenced |= 1 << 2;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbralr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ if (insn_referenced & (1 << 5)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbnolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbeqlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbnelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcblglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbuelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbullr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbgelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbltlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbugelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbuglr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcblelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbgtlr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbulelr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbulr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcbolr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcbeqlr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_FCCi_2 = FLD (in_FCCi_2);
+ referenced |= 1 << 3;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_jmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_calll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_jmpil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_callil (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_call (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_call.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_rett (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_rett.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_rei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_teq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_thi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tnc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tnv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_teq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fteq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftlg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftlt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fto (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tils (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tihi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tic (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tinc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tin (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tip (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tiv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tinv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_tieq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_ICCi_2 = FLD (in_ICCi_2);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftira (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftino (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftine (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftieq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftilg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftiue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftiul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftige (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftilt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftiuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftiug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftile (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftigt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftiule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftiu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ftio (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_ftine.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_FCCi_2 = FLD (in_FCCi_2);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_trap (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_break (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_break.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mtrap (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_andcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_orcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_xorcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nandcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_norcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_andncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_orncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nandncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_norncr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_notcr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_andcr.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ccklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ccknc (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckn (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckp (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cckv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ccknv (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cckeq.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_ICCi_3 = FLD (in_ICCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckra (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckno (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckne (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckeq (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfcklg (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckue (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfcklt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckuge (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckug (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckle (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckgt (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfckule (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfcku (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfcko (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfckne.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ICCi_3 = -1;
+ INT in_FCCi_3 = -1;
+ in_FCCi_3 = FLD (in_FCCi_3);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_check (current_cpu, idesc, 0, referenced, in_ICCi_3, in_FCCi_3);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cjmpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ccalll (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cjmpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ INT in_ICCi_2 = -1;
+ INT in_FCCi_2 = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 4;
+ cycles += frvbf_model_fr450_u_branch (current_cpu, idesc, 0, referenced, in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_ici (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_dci (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_icei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_ici (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_dcei (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_dci (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_dcf (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_dcef (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icei.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_dcf (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_witlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_wdtlb (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_itlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_dtlbi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_icpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_icpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_dcpl (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_icpl.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ in_GRj = FLD (in_GRj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_dcpl (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_icul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_icul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_dcul (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_jmpil.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_GRi = -1;
+ INT in_GRj = -1;
+ in_GRi = FLD (in_GRi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_dcul (current_cpu, idesc, 0, referenced, in_GRi, in_GRj);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_bar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_barrier (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_membar (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_membar (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lrai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_lrad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_tlbpr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cop1 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cop2 (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clrgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_swapi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clrfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clrga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_clrfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_commitgr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_setlos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_commitfr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_commitga (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_commitfa (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fitod (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fitod.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdtoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdtoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfditos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfitos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfitos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fditos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfstoi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdstoi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmovd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfmovs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fnegd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfnegs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fabsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfabss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fsqrtd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfsqrts (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_faddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmuld (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdivd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fcmpd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fcmpd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfcmps.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmaddd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmsubd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fmaddd.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfmadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfmsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cfmas.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fmsd (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfmas (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfmss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_fdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdmulcs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdadds (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdsubs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdmuls (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfddivs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdsads (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_fdmadds.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_nfdcmps (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_nfdcmps.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mhsetlos (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetlos.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRkhi = -1;
+ INT out_FRklo = -1;
+ out_FRklo = FLD (out_FRklo);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mhsethis (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethis.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRkhi = -1;
+ INT out_FRklo = -1;
+ out_FRkhi = FLD (out_FRkhi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mhdsets (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdsets.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mhsetloh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsetloh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRkhi = -1;
+ INT out_FRklo = -1;
+ out_FRklo = FLD (out_FRklo);
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mhsethih (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhsethih.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT out_FRkhi = -1;
+ INT out_FRklo = -1;
+ out_FRkhi = FLD (out_FRkhi);
+ referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_media_hilo (current_cpu, idesc, 0, referenced, out_FRkhi, out_FRklo);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mhdseth (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mhdseth.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmand (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmxor (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmnot (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmand.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 3)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mrotri (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mwcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mwcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mcut (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mcuti (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mcutss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mdcutssi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdcutssi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_FRintk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_FRintk = FLD (out_FRintkeven);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ cycles += frvbf_model_fr450_u_media_4_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_maveh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcut.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_msllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_msrlhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_msrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_msllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_6 (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mdrotli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdrotli.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mcplhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcplhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mcpli (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mwcuti.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_3_dual (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_msaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqsaths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_msathu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mcmpsh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FCCk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FCCk = FLD (out_FCCk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mcmpuh (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mcmpsh.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FCCk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_FCCk = FLD (out_FCCk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_7 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FCCk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mabshs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mabshs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRintj = FLD (in_FRintj);
+ out_FRintk = FLD (out_FRintk);
+ referenced |= 1 << 1;
+ referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_maddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_maddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_msubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_msubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ referenced |= 1 << 0;
+ referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_1 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmqaddhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmqaddhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmqsubhss (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmqsubhus (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqlmths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_1_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqsllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintieven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqsrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_FRintk = -1;
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintieven);
+ out_FRintk = FLD (out_FRintkeven);
+ cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_msubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_2_acc (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mdaddaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mdsubaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_2_acc_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_masaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 4)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_2_add_sub (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mdasaccs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mdasaccs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_ACC40Si = -1;
+ INT out_ACC40Sk = -1;
+ in_ACC40Si = FLD (in_ACC40Si);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 6)) referenced |= 1 << 1;
+ cycles += frvbf_model_fr450_u_media_2_add_sub_dual (current_cpu, idesc, 0, referenced, in_ACC40Si, out_ACC40Sk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqmulxhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mqmulxhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmqmulhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmqmulhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ in_FRinti = FLD (in_FRintieven);
+ in_FRintj = FLD (in_FRintjeven);
+ if (insn_referenced & (1 << 15)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mmachs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mmachu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mmrdhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachs.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Sk = FLD (out_ACC40Sk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_mmrdhu (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmmachu.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ INT in_FRinti = -1;
+ INT in_FRintj = -1;
+ INT out_ACC40Sk = -1;
+ INT out_ACC40Uk = -1;
+ in_FRinti = FLD (in_FRinti);
+ in_FRintj = FLD (in_FRintj);
+ out_ACC40Uk = FLD (out_ACC40Uk);
+ if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
+ if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
+ if (insn_referenced & (1 << 11)) referenced |= 1 << 3;
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_fr450_cmmachs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmmachu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachu.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 2)) referenced |= 1 << 0;
if (insn_referenced & (1 << 3)) referenced |= 1 << 1;
if (insn_referenced & (1 << 13)) referenced |= 1 << 3;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqmachs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqmachu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachu.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 17)) referenced |= 1 << 3;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmqmachs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 19)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmqmachu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachu.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 19)) referenced |= 1 << 3;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqxmachs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqxmacxhs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqmacxhs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 17)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mcpxrs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mcpxru (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mcpxis (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mcpxiu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
if (insn_referenced & (1 << 1)) referenced |= 1 << 1;
if (insn_referenced & (1 << 9)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmcpxrs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmcpxru (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmcpxis (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmcpxiu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
if (insn_referenced & (1 << 1)) referenced |= 1 << 0;
if (insn_referenced & (1 << 2)) referenced |= 1 << 1;
if (insn_referenced & (1 << 11)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqcpxrs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqcpxru (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqcpxis (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mqcpxiu (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmqmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
if (insn_referenced & (1 << 13)) referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
+ cycles += frvbf_model_fr450_u_media_2_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_ACC40Sk, out_ACC40Uk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mexpdhw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT in_FRinti = -1;
INT in_FRintj = -1;
INT out_FRintk = -1;
- cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmexpdhw (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmexpdhw.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT in_FRinti = -1;
INT in_FRintj = -1;
INT out_FRintk = -1;
- cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mexpdhd (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT in_FRinti = -1;
INT out_FRintk = -1;
out_FRintk = FLD (out_FRintkeven);
- cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmexpdhd (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmexpdhd.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT in_FRinti = -1;
INT out_FRintk = -1;
out_FRintk = FLD (out_FRintkeven);
- cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mpackh (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mpackh (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmaddhss.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT in_FRinti = -1;
INT in_FRintj = -1;
INT out_FRintk = -1;
- cycles += frvbf_model_fr400_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_3 (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mdpackh (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdpackh.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRintieven);
in_FRintj = FLD (in_FRintjeven);
out_FRintk = FLD (out_FRintkeven);
- cycles += frvbf_model_fr400_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_3_quad (current_cpu, idesc, 0, referenced, in_FRinti, in_FRintj, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_munpackh (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_munpackh (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_munpackh.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
in_FRinti = FLD (in_FRinti);
out_FRintk = FLD (out_FRintkeven);
if (insn_referenced & (1 << 0)) referenced |= 1 << 0;
- cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mdunpackh (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdunpackh.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mbtoh (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmbtoh.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT in_FRinti = -1;
INT out_FRintk = -1;
out_FRintk = FLD (out_FRintkeven);
- cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmbtoh (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmbtoh.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT in_FRinti = -1;
INT out_FRintk = -1;
out_FRintk = FLD (out_FRintkeven);
- cycles += frvbf_model_fr400_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_dual_expand (current_cpu, idesc, 0, referenced, in_FRinti, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mhtob (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mhtob (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmhtob.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
out_FRintk = FLD (out_FRintk);
in_FRintj = FLD (in_FRintjeven);
referenced |= 1 << 1;
- cycles += frvbf_model_fr400_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmhtob (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmhtob.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
out_FRintk = FLD (out_FRintk);
in_FRintj = FLD (in_FRintjeven);
referenced |= 1 << 1;
- cycles += frvbf_model_fr400_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_dual_htob (current_cpu, idesc, 0, referenced, in_FRintj, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mbtohe (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmbtohe.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_cmbtohe (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmbtohe.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mnop (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mnop (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mclracc_0 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT in_FRintj = -1;
INT out_ACC40Sk = -1;
INT out_FRintk = -1;
- cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mclracc_1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- INT in_ACC40Si = -1;
- INT in_FRintj = -1;
- INT out_ACC40Sk = -1;
- INT out_FRintk = -1;
- cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_4_mclracca (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mrdacc (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mcuti.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
out_FRintk = FLD (out_FRintk);
referenced |= 1 << 0;
referenced |= 1 << 3;
- cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mrdaccg (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mrdaccg.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
out_FRintk = FLD (out_FRintk);
referenced |= 1 << 0;
referenced |= 1 << 3;
- cycles += frvbf_model_fr400_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mwtacc (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_cmmachs.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
INT out_FRintk = -1;
out_ACC40Sk = FLD (out_ACC40Sk);
referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_4 (current_cpu, idesc, 0, referenced, in_ACC40Si, in_FRintj, out_ACC40Sk, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mwtaccg (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mwtaccg.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
out_ACCGk = FLD (out_ACCGk);
referenced |= 1 << 1;
referenced |= 1 << 2;
- cycles += frvbf_model_fr400_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);
+ cycles += frvbf_model_fr450_u_media_4_accg (current_cpu, idesc, 0, referenced, in_ACCGi, in_FRinti, out_ACCGk, out_FRintk);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mcop1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_mcop2 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
-model_fr400_fnop (SIM_CPU *current_cpu, void *sem_arg)
+model_fr450_fnop (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
{
int referenced = 0;
int UNUSED insn_referenced = abuf->written;
- cycles += frvbf_model_fr400_u_exec (current_cpu, idesc, 0, referenced);
+ cycles += frvbf_model_fr450_u_exec (current_cpu, idesc, 0, referenced);
}
return cycles;
#undef FLD
}
static int
+model_simple_lrai (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_lrad (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_tlbpr (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_simple_cop1 (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.fmt_empty.f
}
static int
+model_simple_mqlclrhs (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqlmths (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqsllhi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
+model_simple_mqsrahi (SIM_CPU *current_cpu, void *sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg);
+ const IDESC * UNUSED idesc = abuf->idesc;
+ int cycles = 0;
+ {
+ int referenced = 0;
+ int UNUSED insn_referenced = abuf->written;
+ cycles += frvbf_model_simple_u_exec (current_cpu, idesc, 0, referenced);
+ }
+ return cycles;
+#undef FLD
+}
+
+static int
model_simple_maddaccs (SIM_CPU *current_cpu, void *sem_arg)
{
#define FLD(f) abuf->fields.sfmt_mdasaccs.f
{ FRVBF_INSN_DCUL, model_frv_dcul, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_BAR, model_frv_bar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MEMBAR, model_frv_membar, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAI, model_frv_lrai, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAD, model_frv_lrad, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TLBPR, model_frv_tlbpr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP1, model_frv_cop1, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP2, model_frv_cop2, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGR, model_frv_clrgr, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQADDHUS, model_frv_cmqaddhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHSS, model_frv_cmqsubhss, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHUS, model_frv_cmqsubhus, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLCLRHS, model_frv_mqlclrhs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLMTHS, model_frv_mqlmths, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSLLHI, model_frv_mqsllhi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSRAHI, model_frv_mqsrahi, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MADDACCS, model_frv_maddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MSUBACCS, model_frv_msubaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MDADDACCS, model_frv_mdaddaccs, { { (int) UNIT_FRV_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_DCUL, model_fr550_dcul, { { (int) UNIT_FR550_U_DCUL, 1, 1 } } },
{ FRVBF_INSN_BAR, model_fr550_bar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MEMBAR, model_fr550_membar, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAI, model_fr550_lrai, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAD, model_fr550_lrad, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TLBPR, model_fr550_tlbpr, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP1, model_fr550_cop1, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP2, model_fr550_cop2, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGR, model_fr550_clrgr, { { (int) UNIT_FR550_U_CLRGR, 1, 1 } } },
{ FRVBF_INSN_CMQADDHUS, model_fr550_cmqaddhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHSS, model_fr550_cmqsubhss, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHUS, model_fr550_cmqsubhus, { { (int) UNIT_FR550_U_MEDIA_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQLCLRHS, model_fr550_mqlclrhs, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLMTHS, model_fr550_mqlmths, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSLLHI, model_fr550_mqsllhi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSRAHI, model_fr550_mqsrahi, { { (int) UNIT_FR550_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MADDACCS, model_fr550_maddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } },
{ FRVBF_INSN_MSUBACCS, model_fr550_msubaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC, 1, 1 } } },
{ FRVBF_INSN_MDADDACCS, model_fr550_mdaddaccs, { { (int) UNIT_FR550_U_MEDIA_4_ACC_DUAL, 1, 1 } } },
{ FRVBF_INSN_DCUL, model_fr500_dcul, { { (int) UNIT_FR500_U_DCUL, 1, 1 } } },
{ FRVBF_INSN_BAR, model_fr500_bar, { { (int) UNIT_FR500_U_BARRIER, 1, 1 } } },
{ FRVBF_INSN_MEMBAR, model_fr500_membar, { { (int) UNIT_FR500_U_MEMBAR, 1, 1 } } },
+ { FRVBF_INSN_LRAI, model_fr500_lrai, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAD, model_fr500_lrad, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TLBPR, model_fr500_tlbpr, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP1, model_fr500_cop1, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP2, model_fr500_cop2, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGR, model_fr500_clrgr, { { (int) UNIT_FR500_U_CLRGR, 1, 1 } } },
{ FRVBF_INSN_CMQADDHUS, model_fr500_cmqaddhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHSS, model_fr500_cmqsubhss, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHUS, model_fr500_cmqsubhus, { { (int) UNIT_FR500_U_MEDIA_QUAD_ARITH, 1, 1 } } },
+ { FRVBF_INSN_MQLCLRHS, model_fr500_mqlclrhs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLMTHS, model_fr500_mqlmths, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSLLHI, model_fr500_mqsllhi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSRAHI, model_fr500_mqsrahi, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MADDACCS, model_fr500_maddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MSUBACCS, model_fr500_msubaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MDADDACCS, model_fr500_mdaddaccs, { { (int) UNIT_FR500_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_DCUL, model_tomcat_dcul, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_BAR, model_tomcat_bar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MEMBAR, model_tomcat_membar, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAI, model_tomcat_lrai, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAD, model_tomcat_lrad, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TLBPR, model_tomcat_tlbpr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP1, model_tomcat_cop1, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP2, model_tomcat_cop2, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGR, model_tomcat_clrgr, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQADDHUS, model_tomcat_cmqaddhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHSS, model_tomcat_cmqsubhss, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHUS, model_tomcat_cmqsubhus, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLCLRHS, model_tomcat_mqlclrhs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLMTHS, model_tomcat_mqlmths, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSLLHI, model_tomcat_mqsllhi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSRAHI, model_tomcat_mqsrahi, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MADDACCS, model_tomcat_maddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MSUBACCS, model_tomcat_msubaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MDADDACCS, model_tomcat_mdaddaccs, { { (int) UNIT_TOMCAT_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_DCUL, model_fr400_dcul, { { (int) UNIT_FR400_U_DCUL, 1, 1 } } },
{ FRVBF_INSN_BAR, model_fr400_bar, { { (int) UNIT_FR400_U_BARRIER, 1, 1 } } },
{ FRVBF_INSN_MEMBAR, model_fr400_membar, { { (int) UNIT_FR400_U_MEMBAR, 1, 1 } } },
+ { FRVBF_INSN_LRAI, model_fr400_lrai, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAD, model_fr400_lrad, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TLBPR, model_fr400_tlbpr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP1, model_fr400_cop1, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP2, model_fr400_cop2, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGR, model_fr400_clrgr, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQADDHUS, model_fr400_cmqaddhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHSS, model_fr400_cmqsubhss, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHUS, model_fr400_cmqsubhus, { { (int) UNIT_FR400_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQLCLRHS, model_fr400_mqlclrhs, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLMTHS, model_fr400_mqlmths, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSLLHI, model_fr400_mqsllhi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSRAHI, model_fr400_mqsrahi, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MADDACCS, model_fr400_maddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } },
{ FRVBF_INSN_MSUBACCS, model_fr400_msubaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC, 1, 1 } } },
{ FRVBF_INSN_MDADDACCS, model_fr400_mdaddaccs, { { (int) UNIT_FR400_U_MEDIA_2_ACC_DUAL, 1, 1 } } },
{ FRVBF_INSN_FNOP, model_fr400_fnop, { { (int) UNIT_FR400_U_EXEC, 1, 1 } } },
};
+/* Model timing data for `fr450'. */
+
+static const INSN_TIMING fr450_timing[] = {
+ { FRVBF_INSN_X_INVALID, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_AFTER, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_BEFORE, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_CTI_CHAIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_CHAIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_X_BEGIN, 0, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ADD, model_fr450_add, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUB, model_fr450_sub, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_AND, model_fr450_and, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_OR, model_fr450_or, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_XOR, model_fr450_xor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_NOT, model_fr450_not, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SDIV, model_fr450_sdiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_NSDIV, model_fr450_nsdiv, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_UDIV, model_fr450_udiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_NUDIV, model_fr450_nudiv, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMUL, model_fr450_smul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_UMUL, model_fr450_umul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_SMU, model_fr450_smu, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SMASS, model_fr450_smass, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SMSSS, model_fr450_smsss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SLL, model_fr450_sll, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRL, model_fr450_srl, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRA, model_fr450_sra, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SLASS, model_fr450_slass, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCUTSS, model_fr450_scutss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SCAN, model_fr450_scan, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CADD, model_fr450_cadd, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSUB, model_fr450_csub, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CAND, model_fr450_cand, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_COR, model_fr450_cor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CXOR, model_fr450_cxor, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CNOT, model_fr450_cnot, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSMUL, model_fr450_csmul, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_CSDIV, model_fr450_csdiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_CUDIV, model_fr450_cudiv, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_CSLL, model_fr450_csll, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSRL, model_fr450_csrl, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSRA, model_fr450_csra, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSCAN, model_fr450_cscan, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDCC, model_fr450_addcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBCC, model_fr450_subcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ANDCC, model_fr450_andcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ORCC, model_fr450_orcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_XORCC, model_fr450_xorcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SLLCC, model_fr450_sllcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRLCC, model_fr450_srlcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRACC, model_fr450_sracc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SMULCC, model_fr450_smulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_UMULCC, model_fr450_umulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_CADDCC, model_fr450_caddcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSUBCC, model_fr450_csubcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSMULCC, model_fr450_csmulcc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_CANDCC, model_fr450_candcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CORCC, model_fr450_corcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CXORCC, model_fr450_cxorcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSLLCC, model_fr450_csllcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSRLCC, model_fr450_csrlcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CSRACC, model_fr450_csracc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDX, model_fr450_addx, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBX, model_fr450_subx, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDXCC, model_fr450_addxcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBXCC, model_fr450_subxcc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDSS, model_fr450_addss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBSS, model_fr450_subss, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDI, model_fr450_addi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBI, model_fr450_subi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ANDI, model_fr450_andi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ORI, model_fr450_ori, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_XORI, model_fr450_xori, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SDIVI, model_fr450_sdivi, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_NSDIVI, model_fr450_nsdivi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_UDIVI, model_fr450_udivi, { { (int) UNIT_FR450_U_IDIV, 1, 1 } } },
+ { FRVBF_INSN_NUDIVI, model_fr450_nudivi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SMULI, model_fr450_smuli, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_UMULI, model_fr450_umuli, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_SLLI, model_fr450_slli, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRLI, model_fr450_srli, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRAI, model_fr450_srai, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SCANI, model_fr450_scani, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDICC, model_fr450_addicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBICC, model_fr450_subicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ANDICC, model_fr450_andicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ORICC, model_fr450_oricc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_XORICC, model_fr450_xoricc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SMULICC, model_fr450_smulicc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_UMULICC, model_fr450_umulicc, { { (int) UNIT_FR450_U_IMUL, 1, 1 } } },
+ { FRVBF_INSN_SLLICC, model_fr450_sllicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRLICC, model_fr450_srlicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SRAICC, model_fr450_sraicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDXI, model_fr450_addxi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBXI, model_fr450_subxi, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_ADDXICC, model_fr450_addxicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SUBXICC, model_fr450_subxicc, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CMPB, model_fr450_cmpb, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_CMPBA, model_fr450_cmpba, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_SETLO, model_fr450_setlo, { { (int) UNIT_FR450_U_SET_HILO, 1, 1 } } },
+ { FRVBF_INSN_SETHI, model_fr450_sethi, { { (int) UNIT_FR450_U_SET_HILO, 1, 1 } } },
+ { FRVBF_INSN_SETLOS, model_fr450_setlos, { { (int) UNIT_FR450_U_INTEGER, 1, 1 } } },
+ { FRVBF_INSN_LDSB, model_fr450_ldsb, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUB, model_fr450_ldub, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDSH, model_fr450_ldsh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUH, model_fr450_lduh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LD, model_fr450_ld, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDBF, model_fr450_ldbf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDHF, model_fr450_ldhf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDF, model_fr450_ldf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDC, model_fr450_ldc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDSB, model_fr450_nldsb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDUB, model_fr450_nldub, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDSH, model_fr450_nldsh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDUH, model_fr450_nlduh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLD, model_fr450_nld, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDBF, model_fr450_nldbf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDHF, model_fr450_nldhf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDF, model_fr450_nldf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDD, model_fr450_ldd, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDF, model_fr450_lddf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDC, model_fr450_lddc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDD, model_fr450_nldd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDDF, model_fr450_nlddf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQ, model_fr450_ldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQF, model_fr450_ldqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQC, model_fr450_ldqc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQ, model_fr450_nldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQF, model_fr450_nldqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDSBU, model_fr450_ldsbu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUBU, model_fr450_ldubu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDSHU, model_fr450_ldshu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUHU, model_fr450_lduhu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDU, model_fr450_ldu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDSBU, model_fr450_nldsbu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDUBU, model_fr450_nldubu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDSHU, model_fr450_nldshu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDUHU, model_fr450_nlduhu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDU, model_fr450_nldu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDBFU, model_fr450_ldbfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDHFU, model_fr450_ldhfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDFU, model_fr450_ldfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDCU, model_fr450_ldcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDBFU, model_fr450_nldbfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDHFU, model_fr450_nldhfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDFU, model_fr450_nldfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDDU, model_fr450_lddu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDDU, model_fr450_nlddu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDDFU, model_fr450_lddfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDCU, model_fr450_lddcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDDFU, model_fr450_nlddfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQU, model_fr450_ldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQU, model_fr450_nldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQFU, model_fr450_ldqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQCU, model_fr450_ldqcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQFU, model_fr450_nldqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDSBI, model_fr450_ldsbi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDSHI, model_fr450_ldshi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDI, model_fr450_ldi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUBI, model_fr450_ldubi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDUHI, model_fr450_lduhi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDBFI, model_fr450_ldbfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDHFI, model_fr450_ldhfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDFI, model_fr450_ldfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDSBI, model_fr450_nldsbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDUBI, model_fr450_nldubi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDSHI, model_fr450_nldshi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDUHI, model_fr450_nlduhi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDI, model_fr450_nldi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDBFI, model_fr450_nldbfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDHFI, model_fr450_nldhfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDFI, model_fr450_nldfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDDI, model_fr450_lddi, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_LDDFI, model_fr450_lddfi, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_NLDDI, model_fr450_nlddi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDDFI, model_fr450_nlddfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQI, model_fr450_ldqi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LDQFI, model_fr450_ldqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NLDQFI, model_fr450_nldqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STB, model_fr450_stb, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STH, model_fr450_sth, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_ST, model_fr450_st, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STBF, model_fr450_stbf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHF, model_fr450_sthf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STF, model_fr450_stf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STC, model_fr450_stc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STD, model_fr450_std, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDF, model_fr450_stdf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDC, model_fr450_stdc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQ, model_fr450_stq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQF, model_fr450_stqf, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQC, model_fr450_stqc, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STBU, model_fr450_stbu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHU, model_fr450_sthu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STU, model_fr450_stu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STBFU, model_fr450_stbfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHFU, model_fr450_sthfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STFU, model_fr450_stfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STCU, model_fr450_stcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STDU, model_fr450_stdu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDFU, model_fr450_stdfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDCU, model_fr450_stdcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQU, model_fr450_stqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQFU, model_fr450_stqfu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQCU, model_fr450_stqcu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLDSB, model_fr450_cldsb, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDUB, model_fr450_cldub, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDSH, model_fr450_cldsh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDUH, model_fr450_clduh, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLD, model_fr450_cld, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDBF, model_fr450_cldbf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDHF, model_fr450_cldhf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDF, model_fr450_cldf, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDD, model_fr450_cldd, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDDF, model_fr450_clddf, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDQ, model_fr450_cldq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLDSBU, model_fr450_cldsbu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDUBU, model_fr450_cldubu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDSHU, model_fr450_cldshu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDUHU, model_fr450_clduhu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDU, model_fr450_cldu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDBFU, model_fr450_cldbfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDHFU, model_fr450_cldhfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDFU, model_fr450_cldfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDDU, model_fr450_clddu, { { (int) UNIT_FR450_U_GR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDDFU, model_fr450_clddfu, { { (int) UNIT_FR450_U_FR_LOAD, 1, 1 } } },
+ { FRVBF_INSN_CLDQU, model_fr450_cldqu, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CSTB, model_fr450_cstb, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTH, model_fr450_csth, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CST, model_fr450_cst, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTBF, model_fr450_cstbf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTHF, model_fr450_csthf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTF, model_fr450_cstf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTD, model_fr450_cstd, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTDF, model_fr450_cstdf, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTQ, model_fr450_cstq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CSTBU, model_fr450_cstbu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTHU, model_fr450_csthu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTU, model_fr450_cstu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTBFU, model_fr450_cstbfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTHFU, model_fr450_csthfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTFU, model_fr450_cstfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTDU, model_fr450_cstdu, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_CSTDFU, model_fr450_cstdfu, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STBI, model_fr450_stbi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHI, model_fr450_sthi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STI, model_fr450_sti, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STBFI, model_fr450_stbfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STHFI, model_fr450_sthfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STFI, model_fr450_stfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDI, model_fr450_stdi, { { (int) UNIT_FR450_U_GR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STDFI, model_fr450_stdfi, { { (int) UNIT_FR450_U_FR_STORE, 1, 1 } } },
+ { FRVBF_INSN_STQI, model_fr450_stqi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_STQFI, model_fr450_stqfi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_SWAP, model_fr450_swap, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } },
+ { FRVBF_INSN_SWAPI, model_fr450_swapi, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } },
+ { FRVBF_INSN_CSWAP, model_fr450_cswap, { { (int) UNIT_FR450_U_SWAP, 1, 1 } } },
+ { FRVBF_INSN_MOVGF, model_fr450_movgf, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } },
+ { FRVBF_INSN_MOVFG, model_fr450_movfg, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } },
+ { FRVBF_INSN_MOVGFD, model_fr450_movgfd, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } },
+ { FRVBF_INSN_MOVFGD, model_fr450_movfgd, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } },
+ { FRVBF_INSN_MOVGFQ, model_fr450_movgfq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MOVFGQ, model_fr450_movfgq, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CMOVGF, model_fr450_cmovgf, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } },
+ { FRVBF_INSN_CMOVFG, model_fr450_cmovfg, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } },
+ { FRVBF_INSN_CMOVGFD, model_fr450_cmovgfd, { { (int) UNIT_FR450_U_GR2FR, 1, 1 } } },
+ { FRVBF_INSN_CMOVFGD, model_fr450_cmovfgd, { { (int) UNIT_FR450_U_FR2GR, 1, 1 } } },
+ { FRVBF_INSN_MOVGS, model_fr450_movgs, { { (int) UNIT_FR450_U_GR2SPR, 1, 1 } } },
+ { FRVBF_INSN_MOVSG, model_fr450_movsg, { { (int) UNIT_FR450_U_SPR2GR, 1, 1 } } },
+ { FRVBF_INSN_BRA, model_fr450_bra, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNO, model_fr450_bno, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BEQ, model_fr450_beq, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNE, model_fr450_bne, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLE, model_fr450_ble, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BGT, model_fr450_bgt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLT, model_fr450_blt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BGE, model_fr450_bge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLS, model_fr450_bls, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BHI, model_fr450_bhi, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BC, model_fr450_bc, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNC, model_fr450_bnc, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BN, model_fr450_bn, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BP, model_fr450_bp, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BV, model_fr450_bv, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNV, model_fr450_bnv, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBRA, model_fr450_fbra, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBNO, model_fr450_fbno, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBNE, model_fr450_fbne, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBEQ, model_fr450_fbeq, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLG, model_fr450_fblg, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUE, model_fr450_fbue, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUL, model_fr450_fbul, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBGE, model_fr450_fbge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLT, model_fr450_fblt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUGE, model_fr450_fbuge, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUG, model_fr450_fbug, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLE, model_fr450_fble, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBGT, model_fr450_fbgt, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBULE, model_fr450_fbule, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBU, model_fr450_fbu, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBO, model_fr450_fbo, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCTRLR, model_fr450_bctrlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BRALR, model_fr450_bralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNOLR, model_fr450_bnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BEQLR, model_fr450_beqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNELR, model_fr450_bnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLELR, model_fr450_blelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BGTLR, model_fr450_bgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLTLR, model_fr450_bltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BGELR, model_fr450_bgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BLSLR, model_fr450_blslr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BHILR, model_fr450_bhilr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCLR, model_fr450_bclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNCLR, model_fr450_bnclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNLR, model_fr450_bnlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BPLR, model_fr450_bplr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BVLR, model_fr450_bvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BNVLR, model_fr450_bnvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBRALR, model_fr450_fbralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBNOLR, model_fr450_fbnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBEQLR, model_fr450_fbeqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBNELR, model_fr450_fbnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLGLR, model_fr450_fblglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUELR, model_fr450_fbuelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBULLR, model_fr450_fbullr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBGELR, model_fr450_fbgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLTLR, model_fr450_fbltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUGELR, model_fr450_fbugelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBUGLR, model_fr450_fbuglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBLELR, model_fr450_fblelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBGTLR, model_fr450_fbgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBULELR, model_fr450_fbulelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBULR, model_fr450_fbulr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FBOLR, model_fr450_fbolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCRALR, model_fr450_bcralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNOLR, model_fr450_bcnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCEQLR, model_fr450_bceqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNELR, model_fr450_bcnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCLELR, model_fr450_bclelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCGTLR, model_fr450_bcgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCLTLR, model_fr450_bcltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCGELR, model_fr450_bcgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCLSLR, model_fr450_bclslr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCHILR, model_fr450_bchilr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCCLR, model_fr450_bcclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNCLR, model_fr450_bcnclr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNLR, model_fr450_bcnlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCPLR, model_fr450_bcplr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCVLR, model_fr450_bcvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_BCNVLR, model_fr450_bcnvlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBRALR, model_fr450_fcbralr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBNOLR, model_fr450_fcbnolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBEQLR, model_fr450_fcbeqlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBNELR, model_fr450_fcbnelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBLGLR, model_fr450_fcblglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBUELR, model_fr450_fcbuelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBULLR, model_fr450_fcbullr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBGELR, model_fr450_fcbgelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBLTLR, model_fr450_fcbltlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBUGELR, model_fr450_fcbugelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBUGLR, model_fr450_fcbuglr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBLELR, model_fr450_fcblelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBGTLR, model_fr450_fcbgtlr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBULELR, model_fr450_fcbulelr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBULR, model_fr450_fcbulr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_FCBOLR, model_fr450_fcbolr, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_JMPL, model_fr450_jmpl, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_CALLL, model_fr450_calll, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_JMPIL, model_fr450_jmpil, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_CALLIL, model_fr450_callil, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_CALL, model_fr450_call, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_RETT, model_fr450_rett, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_REI, model_fr450_rei, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TRA, model_fr450_tra, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TNO, model_fr450_tno, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TEQ, model_fr450_teq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TNE, model_fr450_tne, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TLE, model_fr450_tle, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TGT, model_fr450_tgt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TLT, model_fr450_tlt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TGE, model_fr450_tge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TLS, model_fr450_tls, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_THI, model_fr450_thi, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TC, model_fr450_tc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TNC, model_fr450_tnc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TN, model_fr450_tn, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TP, model_fr450_tp, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TV, model_fr450_tv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TNV, model_fr450_tnv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTRA, model_fr450_ftra, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTNO, model_fr450_ftno, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTNE, model_fr450_ftne, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTEQ, model_fr450_fteq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTLG, model_fr450_ftlg, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTUE, model_fr450_ftue, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTUL, model_fr450_ftul, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTGE, model_fr450_ftge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTLT, model_fr450_ftlt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTUGE, model_fr450_ftuge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTUG, model_fr450_ftug, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTLE, model_fr450_ftle, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTGT, model_fr450_ftgt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTULE, model_fr450_ftule, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTU, model_fr450_ftu, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTO, model_fr450_fto, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIRA, model_fr450_tira, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TINO, model_fr450_tino, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIEQ, model_fr450_tieq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TINE, model_fr450_tine, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TILE, model_fr450_tile, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIGT, model_fr450_tigt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TILT, model_fr450_tilt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIGE, model_fr450_tige, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TILS, model_fr450_tils, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIHI, model_fr450_tihi, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIC, model_fr450_tic, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TINC, model_fr450_tinc, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIN, model_fr450_tin, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIP, model_fr450_tip, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TIV, model_fr450_tiv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_TINV, model_fr450_tinv, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIRA, model_fr450_ftira, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FTINO, model_fr450_ftino, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTINE, model_fr450_ftine, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIEQ, model_fr450_ftieq, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTILG, model_fr450_ftilg, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIUE, model_fr450_ftiue, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIUL, model_fr450_ftiul, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIGE, model_fr450_ftige, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTILT, model_fr450_ftilt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIUGE, model_fr450_ftiuge, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIUG, model_fr450_ftiug, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTILE, model_fr450_ftile, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIGT, model_fr450_ftigt, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIULE, model_fr450_ftiule, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIU, model_fr450_ftiu, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_FTIO, model_fr450_ftio, { { (int) UNIT_FR450_U_TRAP, 1, 1 } } },
+ { FRVBF_INSN_BREAK, model_fr450_break, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MTRAP, model_fr450_mtrap, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ANDCR, model_fr450_andcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ORCR, model_fr450_orcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_XORCR, model_fr450_xorcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NANDCR, model_fr450_nandcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NORCR, model_fr450_norcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ANDNCR, model_fr450_andncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ORNCR, model_fr450_orncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NANDNCR, model_fr450_nandncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NORNCR, model_fr450_norncr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NOTCR, model_fr450_notcr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CKRA, model_fr450_ckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKNO, model_fr450_ckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKEQ, model_fr450_ckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKNE, model_fr450_ckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKLE, model_fr450_ckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKGT, model_fr450_ckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKLT, model_fr450_cklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKGE, model_fr450_ckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKLS, model_fr450_ckls, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKHI, model_fr450_ckhi, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKC, model_fr450_ckc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKNC, model_fr450_cknc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKN, model_fr450_ckn, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKP, model_fr450_ckp, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKV, model_fr450_ckv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CKNV, model_fr450_cknv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKRA, model_fr450_fckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKNO, model_fr450_fckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKNE, model_fr450_fckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKEQ, model_fr450_fckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKLG, model_fr450_fcklg, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKUE, model_fr450_fckue, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKUL, model_fr450_fckul, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKGE, model_fr450_fckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKLT, model_fr450_fcklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKUGE, model_fr450_fckuge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKUG, model_fr450_fckug, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKLE, model_fr450_fckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKGT, model_fr450_fckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKULE, model_fr450_fckule, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKU, model_fr450_fcku, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_FCKO, model_fr450_fcko, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKRA, model_fr450_cckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKNO, model_fr450_cckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKEQ, model_fr450_cckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKNE, model_fr450_cckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKLE, model_fr450_cckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKGT, model_fr450_cckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKLT, model_fr450_ccklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKGE, model_fr450_cckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKLS, model_fr450_cckls, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKHI, model_fr450_cckhi, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKC, model_fr450_cckc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKNC, model_fr450_ccknc, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKN, model_fr450_cckn, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKP, model_fr450_cckp, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKV, model_fr450_cckv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CCKNV, model_fr450_ccknv, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKRA, model_fr450_cfckra, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKNO, model_fr450_cfckno, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKNE, model_fr450_cfckne, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKEQ, model_fr450_cfckeq, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKLG, model_fr450_cfcklg, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKUE, model_fr450_cfckue, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKUL, model_fr450_cfckul, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKGE, model_fr450_cfckge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKLT, model_fr450_cfcklt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKUGE, model_fr450_cfckuge, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKUG, model_fr450_cfckug, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKLE, model_fr450_cfckle, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKGT, model_fr450_cfckgt, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKULE, model_fr450_cfckule, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKU, model_fr450_cfcku, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CFCKO, model_fr450_cfcko, { { (int) UNIT_FR450_U_CHECK, 1, 1 } } },
+ { FRVBF_INSN_CJMPL, model_fr450_cjmpl, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_CCALLL, model_fr450_ccalll, { { (int) UNIT_FR450_U_BRANCH, 1, 1 } } },
+ { FRVBF_INSN_ICI, model_fr450_ici, { { (int) UNIT_FR450_U_ICI, 1, 1 } } },
+ { FRVBF_INSN_DCI, model_fr450_dci, { { (int) UNIT_FR450_U_DCI, 1, 1 } } },
+ { FRVBF_INSN_ICEI, model_fr450_icei, { { (int) UNIT_FR450_U_ICI, 1, 1 } } },
+ { FRVBF_INSN_DCEI, model_fr450_dcei, { { (int) UNIT_FR450_U_DCI, 1, 1 } } },
+ { FRVBF_INSN_DCF, model_fr450_dcf, { { (int) UNIT_FR450_U_DCF, 1, 1 } } },
+ { FRVBF_INSN_DCEF, model_fr450_dcef, { { (int) UNIT_FR450_U_DCF, 1, 1 } } },
+ { FRVBF_INSN_WITLB, model_fr450_witlb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_WDTLB, model_fr450_wdtlb, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ITLBI, model_fr450_itlbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_DTLBI, model_fr450_dtlbi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_ICPL, model_fr450_icpl, { { (int) UNIT_FR450_U_ICPL, 1, 1 } } },
+ { FRVBF_INSN_DCPL, model_fr450_dcpl, { { (int) UNIT_FR450_U_DCPL, 1, 1 } } },
+ { FRVBF_INSN_ICUL, model_fr450_icul, { { (int) UNIT_FR450_U_ICUL, 1, 1 } } },
+ { FRVBF_INSN_DCUL, model_fr450_dcul, { { (int) UNIT_FR450_U_DCUL, 1, 1 } } },
+ { FRVBF_INSN_BAR, model_fr450_bar, { { (int) UNIT_FR450_U_BARRIER, 1, 1 } } },
+ { FRVBF_INSN_MEMBAR, model_fr450_membar, { { (int) UNIT_FR450_U_MEMBAR, 1, 1 } } },
+ { FRVBF_INSN_LRAI, model_fr450_lrai, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAD, model_fr450_lrad, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TLBPR, model_fr450_tlbpr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_COP1, model_fr450_cop1, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_COP2, model_fr450_cop2, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLRGR, model_fr450_clrgr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLRFR, model_fr450_clrfr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLRGA, model_fr450_clrga, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CLRFA, model_fr450_clrfa, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_COMMITGR, model_fr450_commitgr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_COMMITFR, model_fr450_commitfr, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_COMMITGA, model_fr450_commitga, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_COMMITFA, model_fr450_commitfa, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FITOS, model_fr450_fitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FSTOI, model_fr450_fstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FITOD, model_fr450_fitod, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDTOI, model_fr450_fdtoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDITOS, model_fr450_fditos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDSTOI, model_fr450_fdstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDITOS, model_fr450_nfditos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDSTOI, model_fr450_nfdstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFITOS, model_fr450_cfitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFSTOI, model_fr450_cfstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFITOS, model_fr450_nfitos, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFSTOI, model_fr450_nfstoi, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMOVS, model_fr450_fmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMOVD, model_fr450_fmovd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDMOVS, model_fr450_fdmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMOVS, model_fr450_cfmovs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FNEGS, model_fr450_fnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FNEGD, model_fr450_fnegd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDNEGS, model_fr450_fdnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFNEGS, model_fr450_cfnegs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FABSS, model_fr450_fabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FABSD, model_fr450_fabsd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDABSS, model_fr450_fdabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFABSS, model_fr450_cfabss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FSQRTS, model_fr450_fsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDSQRTS, model_fr450_fdsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDSQRTS, model_fr450_nfdsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FSQRTD, model_fr450_fsqrtd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFSQRTS, model_fr450_cfsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFSQRTS, model_fr450_nfsqrts, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FADDS, model_fr450_fadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FSUBS, model_fr450_fsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMULS, model_fr450_fmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDIVS, model_fr450_fdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FADDD, model_fr450_faddd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FSUBD, model_fr450_fsubd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMULD, model_fr450_fmuld, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDIVD, model_fr450_fdivd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFADDS, model_fr450_cfadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFSUBS, model_fr450_cfsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMULS, model_fr450_cfmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFDIVS, model_fr450_cfdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFADDS, model_fr450_nfadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFSUBS, model_fr450_nfsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFMULS, model_fr450_nfmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDIVS, model_fr450_nfdivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FCMPS, model_fr450_fcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FCMPD, model_fr450_fcmpd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFCMPS, model_fr450_cfcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDCMPS, model_fr450_fdcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMADDS, model_fr450_fmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMSUBS, model_fr450_fmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMADDD, model_fr450_fmaddd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMSUBD, model_fr450_fmsubd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDMADDS, model_fr450_fdmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDMADDS, model_fr450_nfdmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMADDS, model_fr450_cfmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMSUBS, model_fr450_cfmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFMADDS, model_fr450_nfmadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFMSUBS, model_fr450_nfmsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMAS, model_fr450_fmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMSS, model_fr450_fmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDMAS, model_fr450_fdmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDMSS, model_fr450_fdmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDMAS, model_fr450_nfdmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDMSS, model_fr450_nfdmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMAS, model_fr450_cfmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CFMSS, model_fr450_cfmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMAD, model_fr450_fmad, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FMSD, model_fr450_fmsd, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFMAS, model_fr450_nfmas, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFMSS, model_fr450_nfmss, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDADDS, model_fr450_fdadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDSUBS, model_fr450_fdsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDMULS, model_fr450_fdmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDDIVS, model_fr450_fddivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDSADS, model_fr450_fdsads, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FDMULCS, model_fr450_fdmulcs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDMULCS, model_fr450_nfdmulcs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDADDS, model_fr450_nfdadds, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDSUBS, model_fr450_nfdsubs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDMULS, model_fr450_nfdmuls, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDDIVS, model_fr450_nfddivs, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDSADS, model_fr450_nfdsads, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_NFDCMPS, model_fr450_nfdcmps, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MHSETLOS, model_fr450_mhsetlos, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } },
+ { FRVBF_INSN_MHSETHIS, model_fr450_mhsethis, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } },
+ { FRVBF_INSN_MHDSETS, model_fr450_mhdsets, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MHSETLOH, model_fr450_mhsetloh, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } },
+ { FRVBF_INSN_MHSETHIH, model_fr450_mhsethih, { { (int) UNIT_FR450_U_MEDIA_HILO, 1, 1 } } },
+ { FRVBF_INSN_MHDSETH, model_fr450_mhdseth, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MAND, model_fr450_mand, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MOR, model_fr450_mor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MXOR, model_fr450_mxor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_CMAND, model_fr450_cmand, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_CMOR, model_fr450_cmor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_CMXOR, model_fr450_cmxor, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MNOT, model_fr450_mnot, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_CMNOT, model_fr450_cmnot, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MROTLI, model_fr450_mrotli, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_MROTRI, model_fr450_mrotri, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_MWCUT, model_fr450_mwcut, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_MWCUTI, model_fr450_mwcuti, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_MCUT, model_fr450_mcut, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MCUTI, model_fr450_mcuti, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MCUTSS, model_fr450_mcutss, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MCUTSSI, model_fr450_mcutssi, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MDCUTSSI, model_fr450_mdcutssi, { { (int) UNIT_FR450_U_MEDIA_4_ACC_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MAVEH, model_fr450_maveh, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MSLLHI, model_fr450_msllhi, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_MSRLHI, model_fr450_msrlhi, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_MSRAHI, model_fr450_msrahi, { { (int) UNIT_FR450_U_MEDIA_6, 1, 1 } } },
+ { FRVBF_INSN_MDROTLI, model_fr450_mdrotli, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MCPLHI, model_fr450_mcplhi, { { (int) UNIT_FR450_U_MEDIA_3_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MCPLI, model_fr450_mcpli, { { (int) UNIT_FR450_U_MEDIA_3_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MSATHS, model_fr450_msaths, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MQSATHS, model_fr450_mqsaths, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MSATHU, model_fr450_msathu, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MCMPSH, model_fr450_mcmpsh, { { (int) UNIT_FR450_U_MEDIA_7, 1, 1 } } },
+ { FRVBF_INSN_MCMPUH, model_fr450_mcmpuh, { { (int) UNIT_FR450_U_MEDIA_7, 1, 1 } } },
+ { FRVBF_INSN_MABSHS, model_fr450_mabshs, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MADDHSS, model_fr450_maddhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MADDHUS, model_fr450_maddhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MSUBHSS, model_fr450_msubhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MSUBHUS, model_fr450_msubhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_CMADDHSS, model_fr450_cmaddhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_CMADDHUS, model_fr450_cmaddhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_CMSUBHSS, model_fr450_cmsubhss, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_CMSUBHUS, model_fr450_cmsubhus, { { (int) UNIT_FR450_U_MEDIA_1, 1, 1 } } },
+ { FRVBF_INSN_MQADDHSS, model_fr450_mqaddhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQADDHUS, model_fr450_mqaddhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQSUBHSS, model_fr450_mqsubhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQSUBHUS, model_fr450_mqsubhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQADDHSS, model_fr450_cmqaddhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQADDHUS, model_fr450_cmqaddhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQSUBHSS, model_fr450_cmqsubhss, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQSUBHUS, model_fr450_cmqsubhus, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQLCLRHS, model_fr450_mqlclrhs, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQLMTHS, model_fr450_mqlmths, { { (int) UNIT_FR450_U_MEDIA_1_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQSLLHI, model_fr450_mqsllhi, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQSRAHI, model_fr450_mqsrahi, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MADDACCS, model_fr450_maddaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC, 1, 1 } } },
+ { FRVBF_INSN_MSUBACCS, model_fr450_msubaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC, 1, 1 } } },
+ { FRVBF_INSN_MDADDACCS, model_fr450_mdaddaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MDSUBACCS, model_fr450_mdsubaccs, { { (int) UNIT_FR450_U_MEDIA_2_ACC_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MASACCS, model_fr450_masaccs, { { (int) UNIT_FR450_U_MEDIA_2_ADD_SUB, 1, 1 } } },
+ { FRVBF_INSN_MDASACCS, model_fr450_mdasaccs, { { (int) UNIT_FR450_U_MEDIA_2_ADD_SUB_DUAL, 1, 1 } } },
+ { FRVBF_INSN_MMULHS, model_fr450_mmulhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MMULHU, model_fr450_mmulhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MMULXHS, model_fr450_mmulxhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MMULXHU, model_fr450_mmulxhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_CMMULHS, model_fr450_cmmulhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_CMMULHU, model_fr450_cmmulhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MQMULHS, model_fr450_mqmulhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMULHU, model_fr450_mqmulhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMULXHS, model_fr450_mqmulxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMULXHU, model_fr450_mqmulxhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQMULHS, model_fr450_cmqmulhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQMULHU, model_fr450_cmqmulhu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MMACHS, model_fr450_mmachs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MMACHU, model_fr450_mmachu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MMRDHS, model_fr450_mmrdhs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MMRDHU, model_fr450_mmrdhu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_CMMACHS, model_fr450_cmmachs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_CMMACHU, model_fr450_cmmachu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MQMACHS, model_fr450_mqmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMACHU, model_fr450_mqmachu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQMACHS, model_fr450_cmqmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_CMQMACHU, model_fr450_cmqmachu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQXMACHS, model_fr450_mqxmachs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQXMACXHS, model_fr450_mqxmacxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQMACXHS, model_fr450_mqmacxhs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MCPXRS, model_fr450_mcpxrs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MCPXRU, model_fr450_mcpxru, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MCPXIS, model_fr450_mcpxis, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MCPXIU, model_fr450_mcpxiu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_CMCPXRS, model_fr450_cmcpxrs, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_CMCPXRU, model_fr450_cmcpxru, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_CMCPXIS, model_fr450_cmcpxis, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_CMCPXIU, model_fr450_cmcpxiu, { { (int) UNIT_FR450_U_MEDIA_2, 1, 1 } } },
+ { FRVBF_INSN_MQCPXRS, model_fr450_mqcpxrs, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQCPXRU, model_fr450_mqcpxru, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQCPXIS, model_fr450_mqcpxis, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MQCPXIU, model_fr450_mqcpxiu, { { (int) UNIT_FR450_U_MEDIA_2_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MEXPDHW, model_fr450_mexpdhw, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_CMEXPDHW, model_fr450_cmexpdhw, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_MEXPDHD, model_fr450_mexpdhd, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_CMEXPDHD, model_fr450_cmexpdhd, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_MPACKH, model_fr450_mpackh, { { (int) UNIT_FR450_U_MEDIA_3, 1, 1 } } },
+ { FRVBF_INSN_MDPACKH, model_fr450_mdpackh, { { (int) UNIT_FR450_U_MEDIA_3_QUAD, 1, 1 } } },
+ { FRVBF_INSN_MUNPACKH, model_fr450_munpackh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_MDUNPACKH, model_fr450_mdunpackh, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MBTOH, model_fr450_mbtoh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_CMBTOH, model_fr450_cmbtoh, { { (int) UNIT_FR450_U_MEDIA_DUAL_EXPAND, 1, 1 } } },
+ { FRVBF_INSN_MHTOB, model_fr450_mhtob, { { (int) UNIT_FR450_U_MEDIA_DUAL_HTOB, 1, 1 } } },
+ { FRVBF_INSN_CMHTOB, model_fr450_cmhtob, { { (int) UNIT_FR450_U_MEDIA_DUAL_HTOB, 1, 1 } } },
+ { FRVBF_INSN_MBTOHE, model_fr450_mbtohe, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_CMBTOHE, model_fr450_cmbtohe, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MNOP, model_fr450_mnop, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MCLRACC_0, model_fr450_mclracc_0, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MCLRACC_1, model_fr450_mclracc_1, { { (int) UNIT_FR450_U_MEDIA_4_MCLRACCA, 1, 1 } } },
+ { FRVBF_INSN_MRDACC, model_fr450_mrdacc, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MRDACCG, model_fr450_mrdaccg, { { (int) UNIT_FR450_U_MEDIA_4_ACCG, 1, 1 } } },
+ { FRVBF_INSN_MWTACC, model_fr450_mwtacc, { { (int) UNIT_FR450_U_MEDIA_4, 1, 1 } } },
+ { FRVBF_INSN_MWTACCG, model_fr450_mwtaccg, { { (int) UNIT_FR450_U_MEDIA_4_ACCG, 1, 1 } } },
+ { FRVBF_INSN_MCOP1, model_fr450_mcop1, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MCOP2, model_fr450_mcop2, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_FNOP, model_fr450_fnop, { { (int) UNIT_FR450_U_EXEC, 1, 1 } } },
+};
+
/* Model timing data for `simple'. */
static const INSN_TIMING simple_timing[] = {
{ FRVBF_INSN_DCUL, model_simple_dcul, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_BAR, model_simple_bar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MEMBAR, model_simple_membar, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAI, model_simple_lrai, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_LRAD, model_simple_lrad, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_TLBPR, model_simple_tlbpr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP1, model_simple_cop1, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_COP2, model_simple_cop2, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CLRGR, model_simple_clrgr, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQADDHUS, model_simple_cmqaddhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHSS, model_simple_cmqsubhss, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_CMQSUBHUS, model_simple_cmqsubhus, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLCLRHS, model_simple_mqlclrhs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQLMTHS, model_simple_mqlmths, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSLLHI, model_simple_mqsllhi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
+ { FRVBF_INSN_MQSRAHI, model_simple_mqsrahi, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MADDACCS, model_simple_maddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MSUBACCS, model_simple_msubaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
{ FRVBF_INSN_MDADDACCS, model_simple_mdaddaccs, { { (int) UNIT_SIMPLE_U_EXEC, 1, 1 } } },
}
static void
+fr450_model_init (SIM_CPU *cpu)
+{
+ CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_FR450_DATA));
+}
+
+static void
simple_model_init (SIM_CPU *cpu)
{
CPU_MODEL_DATA (cpu) = (void *) zalloc (sizeof (MODEL_SIMPLE_DATA));
{ 0 }
};
+static const MODEL fr450_models[] =
+{
+ { "fr450", & fr450_mach, MODEL_FR450, TIMING_DATA (& fr450_timing[0]), fr450_model_init },
+ { 0 }
+};
+
static const MODEL simple_models[] =
{
{ "simple", & simple_mach, MODEL_SIMPLE, TIMING_DATA (& simple_timing[0]), simple_model_init },
};
static void
+fr450_init_cpu (SIM_CPU *cpu)
+{
+ CPU_REG_FETCH (cpu) = frvbf_fetch_register;
+ CPU_REG_STORE (cpu) = frvbf_store_register;
+ CPU_PC_FETCH (cpu) = frvbf_h_pc_get;
+ CPU_PC_STORE (cpu) = frvbf_h_pc_set;
+ CPU_GET_IDATA (cpu) = frvbf_get_idata;
+ CPU_MAX_INSNS (cpu) = FRVBF_INSN__MAX;
+ CPU_INSN_NAME (cpu) = cgen_insn_name;
+ CPU_FULL_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#if WITH_FAST
+ CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_fast;
+#else
+ CPU_FAST_ENGINE_FN (cpu) = frvbf_engine_run_full;
+#endif
+}
+
+const MACH fr450_mach =
+{
+ "fr450", "fr450", MACH_FR450,
+ 32, 32, & fr450_models[0], & frvbf_imp_properties,
+ fr450_init_cpu,
+ frvbf_prepare_run
+};
+
+static void
simple_init_cpu (SIM_CPU *cpu)
{
CPU_REG_FETCH (cpu) = frvbf_fetch_register;
--- /dev/null
+/* frv simulator fr450 dependent profiling code.
+
+ Copyright (C) 2001, 2004 Free Software Foundation, Inc.
+ Contributed by Red Hat
+
+This file is part of the GNU simulators.
+
+This program is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License along
+with this program; if not, write to the Free Software Foundation, Inc.,
+59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+*/
+#define WANT_CPU
+#define WANT_CPU_FRVBF
+
+#include "sim-main.h"
+#include "bfd.h"
+
+#if WITH_PROFILE_MODEL_P
+
+#include "profile.h"
+#include "profile-fr400.h"
+
+int
+frvbf_model_fr450_u_exec (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced)
+{
+ return idesc->timing->units[unit_num].done;
+}
+
+int
+frvbf_model_fr450_u_integer (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj, INT out_GRk,
+ INT out_ICCi_1)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_integer (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, out_GRk, out_ICCi_1);
+}
+
+int
+frvbf_model_fr450_u_imul (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* Pass 1 is the same as for fr500. */
+ return frvbf_model_fr500_u_imul (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+
+ /* icc0-icc4 are the upper 4 fields of the CCR. */
+ if (out_ICCi_1 >= 0)
+ out_ICCi_1 += 4;
+
+ /* GRk and IACCi_1 have a latency of 1 cycle. */
+ cycles = idesc->timing->units[unit_num].done;
+ update_GRdouble_latency (cpu, out_GRk, cycles + 1);
+ update_CCR_latency (cpu, out_ICCi_1, cycles + 1);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr450_u_idiv (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj, INT out_GRk, INT out_ICCi_1)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* Pass 1 is the same as for fr500. */
+ return frvbf_model_fr500_u_idiv (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, out_GRk, out_ICCi_1);
+ }
+
+ /* icc0-icc4 are the upper 4 fields of the CCR. */
+ if (out_ICCi_1 >= 0)
+ out_ICCi_1 += 4;
+
+ /* GRk, ICCi_1 and the divider have a latency of 18 cycles */
+ cycles = idesc->timing->units[unit_num].done;
+ update_GR_latency (cpu, out_GRk, cycles + 18);
+ update_CCR_latency (cpu, out_ICCi_1, cycles + 18);
+ update_idiv_resource_latency (cpu, 0, cycles + 18);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr450_u_branch (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT in_ICCi_2, INT in_ICCi_3)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_branch (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, in_ICCi_2, in_ICCi_3);
+}
+
+int
+frvbf_model_fr450_u_trap (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT in_ICCi_2, INT in_FCCi_2)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_trap (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, in_ICCi_2, in_FCCi_2);
+}
+
+int
+frvbf_model_fr450_u_check (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ICCi_3, INT in_FCCi_3)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_check (cpu, idesc, unit_num, referenced,
+ in_ICCi_3, in_FCCi_3);
+}
+
+int
+frvbf_model_fr450_u_set_hilo (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT out_GRkhi, INT out_GRklo)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_set_hilo (cpu, idesc, unit_num, referenced,
+ out_GRkhi, out_GRklo);
+}
+
+int
+frvbf_model_fr450_u_gr_load (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT out_GRk, INT out_GRdoublek)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* Pass 1 is the same as for fr500. */
+ return frvbf_model_fr500_u_fr_load (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, out_GRk,
+ out_GRdoublek);
+ }
+
+ cycles = idesc->timing->units[unit_num].done;
+
+ /* The latency of GRk for a load will depend on how long it takes to retrieve
+ the the data from the cache or memory. */
+ update_GR_latency_for_load (cpu, out_GRk, cycles);
+ update_GRdouble_latency_for_load (cpu, out_GRdoublek, cycles);
+
+ if (CGEN_ATTR_VALUE(idesc, idesc->attrs, CGEN_INSN_NON_EXCEPTING))
+ {
+ /* GNER has a latency of 2 cycles. */
+ update_SPR_latency (cpu, GNER_FOR_GR (out_GRk), cycles + 2);
+ update_SPR_latency (cpu, GNER_FOR_GR (out_GRdoublek), cycles + 2);
+ }
+
+ return cycles;
+}
+
+int
+frvbf_model_fr450_u_gr_store (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT in_GRk, INT in_GRdoublek)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_gr_store (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, in_GRk, in_GRdoublek);
+}
+
+int
+frvbf_model_fr450_u_fr_load (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT out_FRk, INT out_FRdoublek)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, out_FRk, out_FRdoublek);
+}
+
+int
+frvbf_model_fr450_u_fr_store (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj,
+ INT in_FRk, INT in_FRdoublek)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_fr_load (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, in_FRk, in_FRdoublek);
+}
+
+int
+frvbf_model_fr450_u_swap (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj, INT out_GRk)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_swap (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj, out_GRk);
+}
+
+int
+frvbf_model_fr450_u_fr2gr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRk, INT out_GRj)
+{
+ int cycles;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ {
+ /* Pass 1 is the same as for fr400. */
+ return frvbf_model_fr500_u_fr2gr (cpu, idesc, unit_num, referenced,
+ in_FRk, out_GRj);
+ }
+
+ /* The latency of GRj is 1 cycle. */
+ cycles = idesc->timing->units[unit_num].done;
+ update_GR_latency (cpu, out_GRj, cycles + 1);
+
+ return cycles;
+}
+
+int
+frvbf_model_fr450_u_spr2gr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_spr, INT out_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_spr2gr (cpu, idesc, unit_num, referenced,
+ in_spr, out_GRj);
+}
+
+int
+frvbf_model_fr450_u_gr2fr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRj, INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_gr2fr (cpu, idesc, unit_num, referenced,
+ in_GRj, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_gr2spr (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRj, INT out_spr)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_gr2spr (cpu, idesc, unit_num, referenced,
+ in_GRj, out_spr);
+}
+
+int
+frvbf_model_fr450_u_media_1 (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_1 (cpu, idesc, unit_num, referenced,
+ in_FRi, in_FRj, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_1_quad (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_1_quad (cpu, idesc, unit_num, referenced,
+ in_FRi, in_FRj, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_hilo (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT out_FRkhi, INT out_FRklo)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_hilo (cpu, idesc, unit_num, referenced,
+ out_FRkhi, out_FRklo);
+}
+
+int
+frvbf_model_fr450_u_media_2 (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_ACC40Sk, INT out_ACC40Uk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_2 (cpu, idesc, unit_num, referenced,
+ in_FRi, in_FRj, out_ACC40Sk,
+ out_ACC40Uk);
+}
+
+int
+frvbf_model_fr450_u_media_2_quad (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_ACC40Sk, INT out_ACC40Uk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_2_quad (cpu, idesc, unit_num, referenced,
+ in_FRi, in_FRj, out_ACC40Sk,
+ out_ACC40Uk);
+}
+
+int
+frvbf_model_fr450_u_media_2_acc (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_ACC40Sk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_2_acc (cpu, idesc, unit_num, referenced,
+ in_ACC40Si, out_ACC40Sk);
+}
+
+int
+frvbf_model_fr450_u_media_2_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_ACC40Sk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_2_acc_dual (cpu, idesc, unit_num,
+ referenced, in_ACC40Si,
+ out_ACC40Sk);
+}
+
+int
+frvbf_model_fr450_u_media_2_add_sub (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_ACC40Sk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_2_add_sub (cpu, idesc, unit_num,
+ referenced, in_ACC40Si,
+ out_ACC40Sk);
+}
+
+int
+frvbf_model_fr450_u_media_2_add_sub_dual (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_ACC40Sk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_2_add_sub_dual (cpu, idesc, unit_num,
+ referenced, in_ACC40Si,
+ out_ACC40Sk);
+}
+
+int
+frvbf_model_fr450_u_media_3 (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_FRk)
+{
+ /* Modelling is the same as media unit 1. */
+ return frvbf_model_fr450_u_media_1 (cpu, idesc, unit_num, referenced,
+ in_FRi, in_FRj, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_3_dual (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_3_dual (cpu, idesc, unit_num, referenced,
+ in_FRi, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_3_quad (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT in_FRj,
+ INT out_FRk)
+{
+ /* Modelling is the same as media unit 1. */
+ return frvbf_model_fr450_u_media_1_quad (cpu, idesc, unit_num, referenced,
+ in_FRi, in_FRj, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_4 (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT in_FRj,
+ INT out_ACC40Sk, INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_4 (cpu, idesc, unit_num, referenced,
+ in_ACC40Si, in_FRj,
+ out_ACC40Sk, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_4_accg (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACCGi, INT in_FRinti,
+ INT out_ACCGk, INT out_FRintk)
+{
+ /* Modelling is the same as media-4 unit except use accumulator guards
+ as input instead of accumulators. */
+ return frvbf_model_fr450_u_media_4 (cpu, idesc, unit_num, referenced,
+ in_ACCGi, in_FRinti,
+ out_ACCGk, out_FRintk);
+}
+
+int
+frvbf_model_fr450_u_media_4_acc_dual (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_ACC40Si, INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_4_acc_dual (cpu, idesc, unit_num,
+ referenced, in_ACC40Si,
+ out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_4_mclracca (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced)
+{
+ int cycles;
+ int acc;
+ FRV_PROFILE_STATE *ps;
+
+ if (model_insn == FRV_INSN_MODEL_PASS_1)
+ return 0;
+
+ /* The preprocessing can execute right away. */
+ cycles = idesc->timing->units[unit_num].done;
+
+ ps = CPU_PROFILE_STATE (cpu);
+
+ /* The post processing must wait for any pending ACC writes. */
+ ps->post_wait = cycles;
+ for (acc = 0; acc < 4; acc++)
+ post_wait_for_ACC (cpu, acc);
+ for (acc = 8; acc < 12; acc++)
+ post_wait_for_ACC (cpu, acc);
+
+ for (acc = 0; acc < 4; acc++)
+ {
+ update_ACC_latency (cpu, acc, ps->post_wait);
+ update_ACC_ptime (cpu, acc, 2);
+ }
+ for (acc = 8; acc < 12; acc++)
+ {
+ update_ACC_latency (cpu, acc, ps->post_wait);
+ update_ACC_ptime (cpu, acc, 2);
+ }
+
+ return cycles;
+}
+
+int
+frvbf_model_fr450_u_media_6 (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi, INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_6 (cpu, idesc, unit_num, referenced,
+ in_FRi, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_7 (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRinti, INT in_FRintj,
+ INT out_FCCk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_7 (cpu, idesc, unit_num, referenced,
+ in_FRinti, in_FRintj, out_FCCk);
+}
+
+int
+frvbf_model_fr450_u_media_dual_expand (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRi,
+ INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_dual_expand (cpu, idesc, unit_num,
+ referenced, in_FRi, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_media_dual_htob (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_FRj,
+ INT out_FRk)
+{
+ /* Modelling for this unit is the same as for fr400. */
+ return frvbf_model_fr400_u_media_dual_htob (cpu, idesc, unit_num,
+ referenced, in_FRj, out_FRk);
+}
+
+int
+frvbf_model_fr450_u_ici (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_ici (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr450_u_dci (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_dci (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr450_u_dcf (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_dcf (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr450_u_icpl (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_icpl (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr450_u_dcpl (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_dcpl (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr450_u_icul (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_icul (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr450_u_dcul (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced,
+ INT in_GRi, INT in_GRj)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_dcul (cpu, idesc, unit_num, referenced,
+ in_GRi, in_GRj);
+}
+
+int
+frvbf_model_fr450_u_barrier (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_barrier (cpu, idesc, unit_num, referenced);
+}
+
+int
+frvbf_model_fr450_u_membar (SIM_CPU *cpu, const IDESC *idesc,
+ int unit_num, int referenced)
+{
+ /* Modelling for this unit is the same as for fr500. */
+ return frvbf_model_fr500_u_membar (cpu, idesc, unit_num, referenced);
+}
+
+#endif /* WITH_PROFILE_MODEL_P */
reset_gr_flags (SIM_CPU *cpu, INT gr)
{
SIM_DESC sd = CPU_STATE (cpu);
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
fr400_reset_gr_flags (cpu, gr);
/* Other machines have no gr flags right now. */
}
reset_fr_flags (SIM_CPU *cpu, INT fr)
{
SIM_DESC sd = CPU_STATE (cpu);
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
fr400_reset_fr_flags (cpu, fr);
else if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr500)
fr500_reset_fr_flags (cpu, fr);
reset_acc_flags (SIM_CPU *cpu, INT acc)
{
SIM_DESC sd = CPU_STATE (cpu);
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
fr400_reset_acc_flags (cpu, acc);
/* Other machines have no acc flags right now. */
}
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
fr400_model_insn_before (cpu, first_p);
break;
case bfd_mach_fr500:
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
fr400_model_insn_after (cpu, last_p, cycles);
break;
case bfd_mach_fr500:
RESERVED
};
+/* SPR definitions for the fr450 machine.
+ See the FR451 LSI for implementation details. */
+static FRV_SPR_CONTROL_INFO fr450_spr[] =
+{
+ {0x200030fe, 0x200030fc, 0xf00030fd, 0xffffff80, IMPL, SUP}, /* PSR */
+ {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, SUP}, /* PCSR */
+ {0x00000000, 0x00000000, 0xffffffff, 0x00000003, IMPL, SUP}, /* BPCSR */
+ {0x00000000, 0x00000000, 0x0000000f, 0x00000fff, IMPL, SUP}, /* TBR */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffeffe, IMPL, SUP}, /* BPSR */
+
+ /* spr registers 5-15 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000d40, 0x00000d40, 0xcc400fc0, 0x20742ff8, IMPL, SUP}, /* HSR0 */
+
+ /* spr registers 17-255 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* CCR */
+
+ /* spr registers 257-262 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffff0000, IMPL, USER}, /* CCCR */
+
+ /* spr registers 264-271 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000003, 0x00000003, IMPL, USER}, /* LR */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* LCR */
+
+ /* spr registers 274-279 and reserved. */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0H */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, USER}, /* IACC0L */
+
+ /* spr registers 282-287 and reserved. */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x20000021, 0x20000000, 0xa0000000, 0xffffffc2, IMPL, USER}, /* ISR */
+
+ /* spr registers 289-511 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EPCR0 */
+
+ /* spr registers 513-575 are reserved */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000100, 0x00000100, 0x00000100, 0xffffffff, IMPL, SUP}, /* ESR0 */
+
+ /* spr registers 577-589 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESR14 */
+ {0x00000800, 0x00000800, 0x00000800, 0xffffffff, IMPL, SUP},
+
+ /* spr registers 592-672 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* ESFR1 */
+
+ /* spr registers 674-831 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* SCR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP},
+
+ /* spr registers 836-1279 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x01c00000, 0x0fff8fc0, IMPL, USER}, /* MSR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffcd, IMPL, USER},
+
+ /* spr registers 1282-1407 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ /* Accumulators are read-only by the user except for special insns and
+ side effect of other insns. ACC0-3 (1408-1411) and ACC8-11 (1416-1419)
+ are implemented, ACC4-7 are not. */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+
+ RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACC8 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+
+ /* spr registers 1420-1471 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ /* Accumulator guards (1472-1483). See comments above ACC0. */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER}, /* ACCG8 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, USER},
+
+ /* spr registers 1484-1535 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR0 */
+
+ /* spr registers 1537-1550 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* EAR15 */
+
+ /* spr registers 1552-1663 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* IAMLR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* IAMLR7 */
+
+ /* spr registers 1672-1727 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, /* IAMPR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002902, IMPL, SUP}, /* IAMPR7 */
+
+ /* spr registers 1736-1791 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* DAMLR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* DAMLR11 */
+
+ /* spr registers 1804-1855 are reserved */
+ RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP}, /* DAMPR0 */
+ {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000001, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0x00002000, IMPL, SUP}, /* DAMPR11 */
+
+ /* spr registers 1868-1919 are reserved */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000808, 0x00000808, 0x00000808, 0xffffffff, IMPL, SUP}, /* AMCR */
+
+ /* spr registers 1921-1924 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffff00, IMPL, SUP}, /* IAMVR1 */
+ RESERVED,
+ {0x00000000, 0x00000000, 0x00000000, 0xfffff000, IMPL, SUP}, /* DAMVR1 */
+
+ /* spr registers 1928-1935 are reserved */
+ RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xfffff000, IMPL, SUP}, /* CXNR */
+ {0x00000000, 0x00000000, 0x00000000, 0x000007fc, IMPL, SUP}, /* TTBR */
+ {0x00000000, 0x00000000, 0x00000000, 0x00003000, IMPL, SUP}, /* TPLR */
+ {0x00000000, 0x00000000, 0x00000000, 0x000031f0, IMPL, SUP}, /* TPPR */
+ {0x00000000, 0x00000000, 0x00000000, 0x0fffffff, IMPL, SUP}, /* TPXR */
+
+ /* spr registers 1941-1951 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERH */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERL */
+ {0x00000000, 0x00000000, 0x00000000, 0x00000000, IMPL, SUP}, /* TIMERD */
+
+ /* spr registers 1955-2047 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DCR */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* BRR */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* NMAR */
+
+ {0x00000000, 0x00000000, 0x00000000, 0x00000ffe, IMPL, SUP}, /* BTBR */
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* IBAR3 */
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR0 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBAR2 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR00 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR02 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBDR10 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* spr registers 2066-2075 are reserved */
+ RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR00 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* spr registers 2078 and 2079 are reserved */
+ RESERVED, RESERVED,
+
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP}, /* DBMR10 */
+ {0x00000000, 0x00000000, 0x00000000, 0xffffffff, IMPL, SUP},
+
+ /* spr registers 2082-4095 are reserved */
+ RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED, RESERVED, RESERVED, RESERVED, RESERVED,
+ RESERVED,
+};
+
/* Initialize register control for this cpu */
void
frv_register_control_init (SIM_CPU *cpu)
if (sizeof (fr400_spr) != FRV_MAX_SPR * sizeof (*fr400_spr))
abort ();
+ if (sizeof (fr450_spr) != FRV_MAX_SPR * sizeof (*fr450_spr))
+ abort ();
if (sizeof (fr500_spr) != FRV_MAX_SPR * sizeof (*fr500_spr))
abort ();
if (sizeof (fr550_spr) != FRV_MAX_SPR * sizeof (*fr550_spr))
control->cpr = 0;
control->spr = fr550_spr;
return;
+ case bfd_mach_fr450:
+ control->fr = 1;
+ control->cpr = 0;
+ control->spr = fr450_spr;
+ return;
case bfd_mach_fr400:
control->fr = 1;
control->cpr = 0;
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
- /* On the fr400: if this is an unimplemented accumulator, then
- generate an illegal_instruction_interrupt, otherwise no interrupt.
- */
- if (spr >= H_SPR_ACC4 && spr <= H_SPR_ACC63
- || spr >= H_SPR_ACCG4 && spr <= H_SPR_ACCG63)
+ case bfd_mach_fr450:
+ /* On the fr4xx series: if this is an unimplemented accumulator,
+ then generate an illegal_instruction_interrupt, otherwise no
+ interrupt. */
+ if (SPR_IS_ACC (spr))
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
case bfd_mach_fr550:
switch (STATE_ARCHITECTURE (sd)->mach)
{
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
/* On some machines this generates an illegal_instruction interrupt. */
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
#undef FLD
}
+/* lrai: lrai$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lrai) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* lrad: lrad$pack $GRi,$GRk,$LRAE,$LRAD,$LRAS */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,lrad) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
+/* tlbpr: tlbpr$pack $GRi,$GRj,$TLBPRopx,$TLBPRL */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,tlbpr) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.fmt_empty.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+((void) 0); /*nop*/
+
+ return vpc;
+#undef FLD
+}
+
/* cop1: cop1$pack $s6_1,$CPRi,$CPRj,$CPRk */
static SEM_PC
#undef FLD
}
+/* mqlclrhs: mqlclrhs$pack $FRintieven,$FRintjeven,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqlclrhs) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+ HI tmp_a1;
+ HI tmp_a2;
+ HI tmp_a3;
+ HI tmp_a4;
+ HI tmp_b1;
+ HI tmp_b2;
+ HI tmp_b3;
+ HI tmp_b4;
+ {
+ SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+ }
+{
+ tmp_a1 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+ tmp_a2 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+ tmp_b1 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+ tmp_b2 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+ tmp_a3 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+ tmp_a4 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+ tmp_b3 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+ tmp_b4 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+ {
+ UHI opval = (LEUHI (ABSHI (tmp_a1), ABSHI (tmp_b1))) ? (0) : (LEHI (0, tmp_b1)) ? (tmp_a1) : (EQHI (tmp_a1, -32768)) ? (32767) : (NEGHI (tmp_a1));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+ }
+ {
+ UHI opval = (LEUHI (ABSHI (tmp_a2), ABSHI (tmp_b2))) ? (0) : (LEHI (0, tmp_b2)) ? (tmp_a2) : (EQHI (tmp_a2, -32768)) ? (32767) : (NEGHI (tmp_a2));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+ }
+ {
+ UHI opval = (LEUHI (ABSHI (tmp_a3), ABSHI (tmp_b3))) ? (0) : (LEHI (0, tmp_b3)) ? (tmp_a3) : (EQHI (tmp_a3, -32768)) ? (32767) : (NEGHI (tmp_a3));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+ }
+ {
+ UHI opval = (LEUHI (ABSHI (tmp_a4), ABSHI (tmp_b4))) ? (0) : (LEHI (0, tmp_b4)) ? (tmp_a4) : (EQHI (tmp_a4, -32768)) ? (32767) : (NEGHI (tmp_a4));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mqlmths: mqlmths$pack $FRintieven,$FRintjeven,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqlmths) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_cmqaddhss.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ORIF (ANDSI (FLD (f_FRj), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1))))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+ HI tmp_a1;
+ HI tmp_a2;
+ HI tmp_a3;
+ HI tmp_a4;
+ HI tmp_b1;
+ HI tmp_b2;
+ HI tmp_b3;
+ HI tmp_b4;
+ {
+ SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+ }
+{
+ tmp_a1 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+ tmp_a2 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+ tmp_b1 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+ tmp_b2 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (0))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+{
+ tmp_a3 = ADDHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+ tmp_a4 = ADDHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRi)), 0));
+ tmp_b3 = ADDHI (GET_H_FR_HI (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+ tmp_b4 = ADDHI (GET_H_FR_LO (((FLD (f_FRj)) + (1))), MULSI (GET_H_FR_INT (FLD (f_FRj)), 0));
+}
+ {
+ UHI opval = (ANDIF (GTHI (tmp_b1, -32768), GEHI (tmp_a1, ABSHI (tmp_b1)))) ? (tmp_b1) : (GTHI (tmp_a1, NEGHI (ABSHI (tmp_b1)))) ? (tmp_a1) : (EQHI (tmp_b1, -32768)) ? (32767) : (NEGHI (tmp_b1));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+ written |= (1 << 15);
+ TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+ }
+ {
+ UHI opval = (ANDIF (GTHI (tmp_b2, -32768), GEHI (tmp_a2, ABSHI (tmp_b2)))) ? (tmp_b2) : (GTHI (tmp_a2, NEGHI (ABSHI (tmp_b2)))) ? (tmp_a2) : (EQHI (tmp_b2, -32768)) ? (32767) : (NEGHI (tmp_b2));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+ written |= (1 << 17);
+ TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+ }
+ {
+ UHI opval = (ANDIF (GTHI (tmp_b3, -32768), GEHI (tmp_a3, ABSHI (tmp_b3)))) ? (tmp_b3) : (GTHI (tmp_a3, NEGHI (ABSHI (tmp_b3)))) ? (tmp_a3) : (EQHI (tmp_b3, -32768)) ? (32767) : (NEGHI (tmp_b3));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+ written |= (1 << 16);
+ TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+ }
+ {
+ UHI opval = (ANDIF (GTHI (tmp_b4, -32768), GEHI (tmp_a4, ABSHI (tmp_b4)))) ? (tmp_b4) : (GTHI (tmp_a4, NEGHI (ABSHI (tmp_b4)))) ? (tmp_a4) : (EQHI (tmp_b4, -32768)) ? (32767) : (NEGHI (tmp_b4));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+ written |= (1 << 18);
+ TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mqsllhi: mqsllhi$pack $FRintieven,$u6,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqsllhi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+ {
+ SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+ }
+ {
+ SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+ }
+ {
+ UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+ }
+ {
+ UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+ }
+ {
+ UHI opval = SLLHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+ }
+ {
+ UHI opval = SLLHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
+/* mqsrahi: mqsrahi$pack $FRintieven,$u6,$FRintkeven */
+
+static SEM_PC
+SEM_FN_NAME (frvbf,mqsrahi) (SIM_CPU *current_cpu, SEM_ARG sem_arg)
+{
+#define FLD(f) abuf->fields.sfmt_mqsllhi.f
+ ARGBUF *abuf = SEM_ARGBUF (sem_arg);
+ int UNUSED written = 0;
+ IADDR UNUSED pc = abuf->addr;
+ SEM_PC vpc = SEM_NEXT_VPC (sem_arg, pc, 4);
+
+if (ORIF (ANDSI (FLD (f_FRi), SUBSI (2, 1)), ANDSI (FLD (f_FRk), SUBSI (2, 1)))) {
+frvbf_media_register_not_aligned (current_cpu);
+} else {
+{
+ {
+ SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRi)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRi), opval);
+ written |= (1 << 9);
+ TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+ }
+ {
+ SI opval = frv_ref_SI (GET_H_FR_INT (FLD (f_FRk)));
+ sim_queue_fn_si_write (current_cpu, frvbf_h_fr_int_set, FLD (f_FRk), opval);
+ written |= (1 << 10);
+ TRACE_RESULT (current_cpu, abuf, "fr_int", 'x', opval);
+ }
+ {
+ UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (0)), opval);
+ written |= (1 << 11);
+ TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+ }
+ {
+ UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (0))), ANDSI (FLD (f_u6), 15));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (0)), opval);
+ written |= (1 << 13);
+ TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+ }
+ {
+ UHI opval = SRAHI (GET_H_FR_HI (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_hi_set, ((FLD (f_FRk)) + (1)), opval);
+ written |= (1 << 12);
+ TRACE_RESULT (current_cpu, abuf, "fr_hi", 'x', opval);
+ }
+ {
+ UHI opval = SRAHI (GET_H_FR_LO (((FLD (f_FRi)) + (1))), ANDSI (FLD (f_u6), 15));
+ sim_queue_fn_hi_write (current_cpu, frvbf_h_fr_lo_set, ((FLD (f_FRk)) + (1)), opval);
+ written |= (1 << 14);
+ TRACE_RESULT (current_cpu, abuf, "fr_lo", 'x', opval);
+ }
+}
+}
+
+ abuf->written = written;
+ return vpc;
+#undef FLD
+}
+
/* maddaccs: maddaccs$pack $ACC40Si,$ACC40Sk */
static SEM_PC
{ FRVBF_INSN_DCUL, SEM_FN_NAME (frvbf,dcul) },
{ FRVBF_INSN_BAR, SEM_FN_NAME (frvbf,bar) },
{ FRVBF_INSN_MEMBAR, SEM_FN_NAME (frvbf,membar) },
+ { FRVBF_INSN_LRAI, SEM_FN_NAME (frvbf,lrai) },
+ { FRVBF_INSN_LRAD, SEM_FN_NAME (frvbf,lrad) },
+ { FRVBF_INSN_TLBPR, SEM_FN_NAME (frvbf,tlbpr) },
{ FRVBF_INSN_COP1, SEM_FN_NAME (frvbf,cop1) },
{ FRVBF_INSN_COP2, SEM_FN_NAME (frvbf,cop2) },
{ FRVBF_INSN_CLRGR, SEM_FN_NAME (frvbf,clrgr) },
{ FRVBF_INSN_CMQADDHUS, SEM_FN_NAME (frvbf,cmqaddhus) },
{ FRVBF_INSN_CMQSUBHSS, SEM_FN_NAME (frvbf,cmqsubhss) },
{ FRVBF_INSN_CMQSUBHUS, SEM_FN_NAME (frvbf,cmqsubhus) },
+ { FRVBF_INSN_MQLCLRHS, SEM_FN_NAME (frvbf,mqlclrhs) },
+ { FRVBF_INSN_MQLMTHS, SEM_FN_NAME (frvbf,mqlmths) },
+ { FRVBF_INSN_MQSLLHI, SEM_FN_NAME (frvbf,mqsllhi) },
+ { FRVBF_INSN_MQSRAHI, SEM_FN_NAME (frvbf,mqsrahi) },
{ FRVBF_INSN_MADDACCS, SEM_FN_NAME (frvbf,maddaccs) },
{ FRVBF_INSN_MSUBACCS, SEM_FN_NAME (frvbf,msubaccs) },
{ FRVBF_INSN_MDADDACCS, SEM_FN_NAME (frvbf,mdaddaccs) },
{
if (sig == sim_core_unaligned_signal)
{
- if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400)
+ if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr400
+ || STATE_ARCHITECTURE (sd)->mach == bfd_mach_fr450)
frv_queue_data_access_error_interrupt (current_cpu, addr);
else
frv_queue_mem_address_not_aligned_interrupt (current_cpu, addr);
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
+ /* Note: there is a discrepancy between V2.2 of the FR400
+ instruction manual and the various FR4xx LSI specs. The former
+ claims that unaligned registers cause an mp_exception while the
+ latter say it's an illegal_instruction. The LSI specs appear
+ to be correct since MTT is fixed at 1. */
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
+ /* See comment in frvbf_cr_not_aligned(). */
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
/* On some machines this generates an illegal_instruction interrupt. */
switch (STATE_ARCHITECTURE (sd)->mach)
{
+ /* See comment in frvbf_cr_not_aligned(). */
case bfd_mach_fr400:
+ case bfd_mach_fr450:
case bfd_mach_fr550:
frv_queue_program_interrupt (current_cpu, FRV_ILLEGAL_INSTRUCTION);
break;
2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+ * sim/frv/allinsn.exp (all_machs): Add fr405 and fr450.
+ * sim/fr400/allinsn.exp (all_machs): Likewise.
+ * sim/fr400/addss.cgs (mach): Change to "fr405 fr450".
+ * sim/fr400/scutss.cgs (mach): Likewise.
+ * sim/fr400/slass.cgs (mach): Likewise.
+ * sim/fr400/smass.cgs (mach): Likewise.
+ * sim/fr400/smsss.cgs (mach): Likewise.
+ * sim/fr400/smu.cgs (mach): Likewise.
+ * sim/fr400/subss.cgs (mach): Likewise.
+ * sim/interrupts/fp_exception.cgs: Replace fmadds with .word.
+ * sim/interrupts/fp_exception-fr550.cgs: Likewise.
+ * sim/frv/mqlclrhs.cgs: New test.
+ * sim/frv/mqlmths.cgs: New test.
+ * sim/frv/mqsllhi.cgs: New test.
+ * sim/frv/mqsrahi.cgs: New test.
+
+2004-03-01 Richard Sandiford <rsandifo@redhat.com>
+
* sim/frv/fr400/scutss.cgs: Fix tests to account for rounding.
Add some new ones.
# load support procs (none yet)
# load_lib cgen.exp
# all machines
- set all_machs "frv fr500 fr550 fr400"
+ set all_machs "frv fr500 fr550 fr400 fr405 fr450"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".
# frv testcase for addss $GRi,$GRj,$GRk
-# mach: fr400
+# mach: fr405 fr450
.include "../testutils.inc"
# load support procs (none yet)
# load_lib cgen.exp
# all machines
- set all_machs "fr400 fr550"
+ set all_machs "fr400 fr405 fr450 fr550"
set cpu_option -mcpu
# The .cgs suffix is for "cgen .s".
# frv testcase for scutss $FRj,$FRk
-# mach: fr400
+# mach: fr405 fr450
.include "../testutils.inc"
# frv testcase for slass $GRi,$GRj,$GRk
-# mach: fr400
+# mach: fr405 fr450
.include "../testutils.inc"
# frv testcase for smass $GRi,$GRj
-# mach: fr400
+# mach: fr405 fr450
.include "../testutils.inc"
# frv testcase for smsss $GRi,$GRj
-# mach: fr400
+# mach: fr405 fr450
.include "../testutils.inc"
# frv testcase for smu $GRi,$GRj
-# mach: fr400
+# mach: fr405 fr450
.include "../testutils.inc"
# frv testcase for subss $GRi,$GRj,$GRk
-# mach: fr400
+# mach: fr405 fr450
.include "../testutils.inc"
set_spr_addr ok1,lr
set_gr_immed 4,gr20 ; PC increment
-bad: fmadds fr16,fr4,fr1 ; unimplemented
+bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented)
test_gr_immed 4,gr15
and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception
set_spr_addr ok1,lr
set_gr_immed 4,gr20 ; PC increment
-bad: fmadds fr16,fr4,fr1 ; unimplemented
+bad: .word 0x83e502c4 ; fmadds fr16,fr4,fr1 (unimplemented)
test_gr_immed 4,gr15
and_spr_immed 0xfbffffff,fsr0 ; disable div/0 fp_exception
--- /dev/null
+# frv testcase for mqlclrhs $FRi,$FRj,$FRj
+# mach: fr450
+
+ .include "testutils.inc"
+
+ start
+
+ .global mqlclrhs
+mqlclrhs:
+ set_fr_iimmed 0x1000,0x2000,fr4
+ set_fr_iimmed 0xe800,0xd800,fr5
+ set_fr_iimmed 0x0800,0x0800,fr6
+ set_fr_iimmed 0x0800,0x0800,fr7
+ mqlclrhs fr4,fr6,fr8
+ test_fr_limmed 0x1000,0x2000,fr8
+ test_fr_limmed 0xe800,0xd800,fr9
+
+ set_fr_iimmed 0x1000,0x2000,fr4
+ set_fr_iimmed 0xe800,0xd800,fr5
+ set_fr_iimmed 0xf800,0xf800,fr6
+ set_fr_iimmed 0xf800,0xf800,fr7
+ mqlclrhs fr4,fr6,fr8
+ test_fr_limmed 0xf000,0xe000,fr8
+ test_fr_limmed 0x1800,0x2800,fr9
+
+ set_fr_iimmed 0x1000,0x1000,fr4
+ set_fr_iimmed 0x1000,0x1000,fr5
+ set_fr_iimmed 0xf000,0xf800,fr6
+ set_fr_iimmed 0x0800,0x1000,fr7
+ mqlclrhs fr4,fr6,fr8
+ test_fr_limmed 0x0000,0xf000,fr8
+ test_fr_limmed 0x1000,0x0000,fr9
+
+ set_fr_iimmed 0xf000,0xf000,fr4
+ set_fr_iimmed 0xf000,0xf000,fr5
+ set_fr_iimmed 0xf000,0xf800,fr6
+ set_fr_iimmed 0x0800,0x1000,fr7
+ mqlclrhs fr4,fr6,fr8
+ test_fr_limmed 0x0000,0x1000,fr8
+ test_fr_limmed 0xf000,0x0000,fr9
+
+ set_fr_iimmed 0x8000,0x8000,fr4
+ set_fr_iimmed 0x8000,0x8000,fr5
+ set_fr_iimmed 0x8000,0x7fff,fr6
+ set_fr_iimmed 0x8001,0x0000,fr7
+ mqlclrhs fr4,fr6,fr8
+ test_fr_limmed 0x0000,0x8000,fr8
+ test_fr_limmed 0x7fff,0x8000,fr9
+
+ set_fr_iimmed 0x7fff,0x7fff,fr4
+ set_fr_iimmed 0x7fff,0x7fff,fr5
+ set_fr_iimmed 0x8000,0x7fff,fr6
+ set_fr_iimmed 0x8001,0x0000,fr7
+ mqlclrhs fr4,fr6,fr8
+ test_fr_limmed 0x0000,0x0000,fr8
+ test_fr_limmed 0x0000,0x7fff,fr9
+
+ set_fr_iimmed 0x8001,0x8001,fr4
+ set_fr_iimmed 0x8001,0x8001,fr5
+ set_fr_iimmed 0x8000,0x7fff,fr6
+ set_fr_iimmed 0x8001,0x0000,fr7
+ mqlclrhs fr4,fr6,fr8
+ test_fr_limmed 0x0000,0x0000,fr8
+ test_fr_limmed 0x0000,0x8001,fr9
+
+ set_fr_iimmed 0x8000,0x8000,fr4
+ set_fr_iimmed 0x0001,0xffff,fr5
+ set_fr_iimmed 0x0001,0xffff,fr6
+ set_fr_iimmed 0x8000,0x8000,fr7
+ mqlclrhs fr4,fr6,fr8
+ test_fr_limmed 0x8000,0x7fff,fr8
+ test_fr_limmed 0x0000,0x0000,fr9
+
+ pass
--- /dev/null
+# frv testcase for mqlmths $FRi,$FRj,$FRj
+# mach: fr450
+
+ .include "testutils.inc"
+
+ start
+
+ .global mqlmths
+mqlmths:
+ set_fr_iimmed 0x1000,0x2000,fr4
+ set_fr_iimmed 0xe800,0xd800,fr5
+ set_fr_iimmed 0x0800,0x0800,fr6
+ set_fr_iimmed 0x0800,0x0800,fr7
+ mqlmths fr4,fr6,fr8
+ test_fr_limmed 0x0800,0x0800,fr8
+ test_fr_limmed 0xf800,0xf800,fr9
+
+ set_fr_iimmed 0x1000,0x2000,fr4
+ set_fr_iimmed 0xe800,0xd800,fr5
+ set_fr_iimmed 0xf800,0xf800,fr6
+ set_fr_iimmed 0xf800,0xf800,fr7
+ mqlmths fr4,fr6,fr8
+ test_fr_limmed 0xf800,0xf800,fr8
+ test_fr_limmed 0x0800,0x0800,fr9
+
+ set_fr_iimmed 0x1000,0x1000,fr4
+ set_fr_iimmed 0x1000,0x1000,fr5
+ set_fr_iimmed 0xe800,0xf800,fr6
+ set_fr_iimmed 0x0800,0x1800,fr7
+ mqlmths fr4,fr6,fr8
+ test_fr_limmed 0x1000,0xf800,fr8
+ test_fr_limmed 0x0800,0x1000,fr9
+
+ set_fr_iimmed 0xf000,0xf000,fr4
+ set_fr_iimmed 0xf000,0xf000,fr5
+ set_fr_iimmed 0xe800,0xf800,fr6
+ set_fr_iimmed 0x0800,0x1800,fr7
+ mqlmths fr4,fr6,fr8
+ test_fr_limmed 0xf000,0x0800,fr8
+ test_fr_limmed 0xf800,0xf000,fr9
+
+ set_fr_iimmed 0x8000,0x8000,fr4
+ set_fr_iimmed 0x8000,0x8000,fr5
+ set_fr_iimmed 0x8000,0x7fff,fr6
+ set_fr_iimmed 0x8001,0x0000,fr7
+ mqlmths fr4,fr6,fr8
+ test_fr_limmed 0x7fff,0x8001,fr8
+ test_fr_limmed 0x7fff,0x0000,fr9
+
+ set_fr_iimmed 0x7fff,0x7fff,fr4
+ set_fr_iimmed 0x7fff,0x7fff,fr5
+ set_fr_iimmed 0x8000,0x7fff,fr6
+ set_fr_iimmed 0x8001,0x0000,fr7
+ mqlmths fr4,fr6,fr8
+ test_fr_limmed 0x7fff,0x7fff,fr8
+ test_fr_limmed 0x8001,0x0000,fr9
+
+ set_fr_iimmed 0x8001,0x8001,fr4
+ set_fr_iimmed 0x8001,0x8001,fr5
+ set_fr_iimmed 0x8000,0x7fff,fr6
+ set_fr_iimmed 0x8001,0x0000,fr7
+ mqlmths fr4,fr6,fr8
+ test_fr_limmed 0x8001,0x8001,fr8
+ test_fr_limmed 0x7fff,0x0000,fr9
+
+ set_fr_iimmed 0x8000,0x8000,fr4
+ set_fr_iimmed 0x0001,0xffff,fr5
+ set_fr_iimmed 0x0001,0xffff,fr6
+ set_fr_iimmed 0x8000,0x8000,fr7
+ mqlmths fr4,fr6,fr8
+ test_fr_limmed 0xffff,0x0001,fr8
+ test_fr_limmed 0x0001,0xffff,fr9
+
+ pass
--- /dev/null
+# frv testcase for mqsllhi $FRi,#u6,$FRj
+# mach: fr450
+
+ .include "testutils.inc"
+
+ start
+
+ .global mqsllhi
+mqsllhi:
+ set_fr_iimmed 0x0001,0x0002,fr4
+ set_fr_iimmed 0x0003,0x0004,fr5
+ mqsllhi fr4,#1,fr6
+ test_fr_limmed 0x0002,0x0004,fr6
+ test_fr_limmed 0x0006,0x0008,fr7
+
+ set_fr_iimmed 0xffff,0xfffe,fr4
+ set_fr_iimmed 0xfffc,0xfff8,fr5
+ mqsllhi fr4,#1,fr6
+ test_fr_limmed 0xfffe,0xfffc,fr6
+ test_fr_limmed 0xfff8,0xfff0,fr7
+
+ set_fr_iimmed 0xffff,0xfffe,fr4
+ set_fr_iimmed 0xfffc,0xfff8,fr5
+ mqsllhi fr4,#12,fr6
+ test_fr_limmed 0xf000,0xe000,fr6
+ test_fr_limmed 0xc000,0x8000,fr7
+
+ set_fr_iimmed 0x1234,0x5678,fr4
+ set_fr_iimmed 0x9abc,0xdef0,fr5
+ mqsllhi fr4,#12,fr6
+ test_fr_limmed 0x4000,0x8000,fr6
+ test_fr_limmed 0xc000,0x0000,fr7
+
+ set_fr_iimmed 0x1234,0x5678,fr4
+ set_fr_iimmed 0x9abc,0xdef0,fr5
+ mqsllhi fr4,#16,fr6
+ test_fr_limmed 0x1234,0x5678,fr6
+ test_fr_limmed 0x9abc,0xdef0,fr7
+
+ pass
--- /dev/null
+# frv testcase for mqsrahi $FRi,#u6,$FRj
+# mach: fr450
+
+ .include "testutils.inc"
+
+ start
+
+ .global mqsrahi
+mqsrahi:
+ set_fr_iimmed 0x0001,0x0002,fr4
+ set_fr_iimmed 0x0003,0x0004,fr5
+ mqsrahi fr4,#1,fr6
+ test_fr_limmed 0x0000,0x0001,fr6
+ test_fr_limmed 0x0001,0x0002,fr7
+
+ set_fr_iimmed 0xffff,0xfffe,fr4
+ set_fr_iimmed 0xfffc,0xfff8,fr5
+ mqsrahi fr4,#1,fr6
+ test_fr_limmed 0xffff,0xffff,fr6
+ test_fr_limmed 0xfffe,0xfffc,fr7
+
+ set_fr_iimmed 0x8000,0xc000,fr4
+ set_fr_iimmed 0xe000,0xf000,fr5
+ mqsrahi fr4,#12,fr6
+ test_fr_limmed 0xfff8,0xfffc,fr6
+ test_fr_limmed 0xfffe,0xffff,fr7
+
+ set_fr_iimmed 0x1234,0x5678,fr4
+ set_fr_iimmed 0x9abc,0xdef0,fr5
+ mqsrahi fr4,#12,fr6
+ test_fr_limmed 0x0001,0x0005,fr6
+ test_fr_limmed 0xfff9,0xfffd,fr7
+
+ set_fr_iimmed 0x1234,0x5678,fr4
+ set_fr_iimmed 0x9abc,0xdef0,fr5
+ mqsrahi fr4,#16,fr6
+ test_fr_limmed 0x1234,0x5678,fr6
+ test_fr_limmed 0x9abc,0xdef0,fr7
+
+ pass
OSDN Git Service
