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clk: mmp2: fix link error without mmp2
authorArnd Bergmann <arnd@arndb.de>
Wed, 8 Apr 2020 16:05:07 +0000 (18:05 +0200)
committerStephen Boyd <sboyd@kernel.org>
Mon, 13 Apr 2020 19:20:06 +0000 (12:20 -0700)
The newly added function is only built into the kernel if mmp2
is enabled, causing a link error otherwise.

arm-linux-gnueabi-ld: drivers/clk/mmp/clk.o: in function `mmp_register_pll_clks':
clk.c:(.text+0x6dc): undefined reference to `mmp_clk_register_pll'

Move it to a different file to get it to link.

Fixes: 5d34d0b32d6c ("clk: mmp2: Add support for PLL clock sources")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lkml.kernel.org/r/20200408160518.2798571-1-arnd@arndb.de
Reported-by: Guenter Roeck <linux@roeck-us.net>
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
drivers/clk/mmp/clk-pll.c
drivers/clk/mmp/clk.c
drivers/clk/mmp/clk.h

index 7077be2..962014c 100644 (file)
@@ -97,7 +97,7 @@ static const struct clk_ops mmp_clk_pll_ops = {
        .recalc_rate = mmp_clk_pll_recalc_rate,
 };
 
-struct clk *mmp_clk_register_pll(char *name,
+static struct clk *mmp_clk_register_pll(char *name,
                        unsigned long default_rate,
                        void __iomem *enable_reg, u32 enable,
                        void __iomem *reg, u8 shift,
@@ -137,3 +137,34 @@ struct clk *mmp_clk_register_pll(char *name,
 
        return clk;
 }
+
+void mmp_register_pll_clks(struct mmp_clk_unit *unit,
+                       struct mmp_param_pll_clk *clks,
+                       void __iomem *base, int size)
+{
+       struct clk *clk;
+       int i;
+
+       for (i = 0; i < size; i++) {
+               void __iomem *reg = NULL;
+
+               if (clks[i].offset)
+                       reg = base + clks[i].offset;
+
+               clk = mmp_clk_register_pll(clks[i].name,
+                                       clks[i].default_rate,
+                                       base + clks[i].enable_offset,
+                                       clks[i].enable,
+                                       reg, clks[i].shift,
+                                       clks[i].input_rate,
+                                       base + clks[i].postdiv_offset,
+                                       clks[i].postdiv_shift);
+               if (IS_ERR(clk)) {
+                       pr_err("%s: failed to register clock %s\n",
+                              __func__, clks[i].name);
+                       continue;
+               }
+               if (clks[i].id)
+                       unit->clk_table[clks[i].id] = clk;
+       }
+}
index 3171236..ca7d37e 100644 (file)
@@ -176,37 +176,6 @@ void mmp_register_div_clks(struct mmp_clk_unit *unit,
        }
 }
 
-void mmp_register_pll_clks(struct mmp_clk_unit *unit,
-                       struct mmp_param_pll_clk *clks,
-                       void __iomem *base, int size)
-{
-       struct clk *clk;
-       int i;
-
-       for (i = 0; i < size; i++) {
-               void __iomem *reg = NULL;
-
-               if (clks[i].offset)
-                       reg = base + clks[i].offset;
-
-               clk = mmp_clk_register_pll(clks[i].name,
-                                       clks[i].default_rate,
-                                       base + clks[i].enable_offset,
-                                       clks[i].enable,
-                                       reg, clks[i].shift,
-                                       clks[i].input_rate,
-                                       base + clks[i].postdiv_offset,
-                                       clks[i].postdiv_shift);
-               if (IS_ERR(clk)) {
-                       pr_err("%s: failed to register clock %s\n",
-                              __func__, clks[i].name);
-                       continue;
-               }
-               if (clks[i].id)
-                       unit->clk_table[clks[i].id] = clk;
-       }
-}
-
 void mmp_clk_add(struct mmp_clk_unit *unit, unsigned int id,
                        struct clk *clk)
 {
index 971b4d6..20dc1e5 100644 (file)
@@ -238,13 +238,6 @@ void mmp_register_pll_clks(struct mmp_clk_unit *unit,
                        struct mmp_param_pll_clk *clks,
                        void __iomem *base, int size);
 
-extern struct clk *mmp_clk_register_pll(char *name,
-                       unsigned long default_rate,
-                       void __iomem *enable_reg, u32 enable,
-                       void __iomem *reg, u8 shift,
-                       unsigned long input_rate,
-                       void __iomem *postdiv_reg, u8 postdiv_shift);
-
 #define DEFINE_MIX_REG_INFO(w_d, s_d, w_m, s_m, fc)    \
 {                                                      \
        .width_div = (w_d),                             \