render x, y reg set.

diff --git a/de0_cv_nes/chip_selector.vhd b/de0_cv_nes/chip_selector.vhd
index 98692bd..f38f9bc 100644 (file)
--- a/de0_cv_nes/chip_selector.vhd
+++ b/de0_cv_nes/chip_selector.vhd
@@ -12,14 +12,14 @@ entity clock_selector is
                 pi_rst_n        : in std_logic;\r
                 pi_base_clk     : in std_logic;\r
                 po_cpu_en       : out std_logic_vector (7 downto 0);\r
-                po_ppu_en       : out std_logic_vector (3 downto 0)\r
+                po_rnd_en       : out std_logic_vector (3 downto 0)\r
         );
 end clock_selector;
 
 architecture rtl of clock_selector is\r
 \r
 signal reg_cpu_en       : std_logic_vector (7 downto 0);\r
-signal reg_ppu_en       : std_logic_vector (3 downto 0);\r
+signal reg_rnd_en       : std_logic_vector (3 downto 0);\r
 \r
 begin
     --Actual NES base clock =  21.477272 MHz
@@ -36,7 +36,6 @@ begin
     --emu ppu clock = base clock / 4
 \r
     po_cpu_en <= reg_cpu_en;\r
-    po_ppu_en <= reg_ppu_en;\r
     \r
     cpu_clk_p : process (pi_rst_n, pi_base_clk)\r
     variable ref_cnt : integer range 0 to 31;\r
@@ -75,27 +74,30 @@ begin
         end if;\r
     end process;\r
 \r
+    --render clock timing enabler.\r
+    po_rnd_en <= reg_rnd_en;\r
+\r
     ppu_clk_p : process (pi_rst_n, pi_base_clk)\r
-    variable ref_cnt : integer range 0 to 15;\r
+    variable ref_cnt : integer range 0 to 3;\r
     begin\r
         if (pi_rst_n = '0') then\r
-            reg_ppu_en <= (others => '0');\r
+            reg_rnd_en <= (others => '0');\r
             ref_cnt := 0;\r
         else\r
             if (rising_edge(pi_base_clk)) then\r
                 if (ref_cnt = 0) then\r
-                    reg_ppu_en <= "0001";\r
-                elsif (ref_cnt = 4) then\r
-                    reg_ppu_en <= "0010";\r
-                elsif (ref_cnt = 8) then\r
-                    reg_ppu_en <= "0100";\r
-                elsif (ref_cnt = 12) then\r
-                    reg_ppu_en <= "1000";\r
+                    reg_rnd_en <= "0001";\r
+                elsif (ref_cnt = 1) then\r
+                    reg_rnd_en <= "0010";\r
+                elsif (ref_cnt = 2) then\r
+                    reg_rnd_en <= "0100";\r
+                elsif (ref_cnt = 3) then\r
+                    reg_rnd_en <= "1000";\r
                 else\r
-                    reg_ppu_en <= "0000";\r
+                    reg_rnd_en <= "0000";\r
                 end if;\r
                 \r
-                if (ref_cnt = 15) then\r
+                if (ref_cnt = 3) then\r
                     ref_cnt := 0;\r
                 else\r
                     ref_cnt := ref_cnt + 1;\r

diff --git a/de0_cv_nes/de0_cv_nes.vhd b/de0_cv_nes/de0_cv_nes.vhd
index f0cf392..7fa3f56 100644 (file)
--- a/de0_cv_nes/de0_cv_nes.vhd
+++ b/de0_cv_nes/de0_cv_nes.vhd
@@ -46,7 +46,7 @@ architecture rtl of de0_cv_nes is
                 pi_rst_n        : in std_logic;\r
                 pi_base_clk     : in std_logic;\r
                 po_cpu_en       : out std_logic_vector (7 downto 0);\r
-                po_ppu_en       : out std_logic_vector (3 downto 0)\r
+                po_rnd_en       : out std_logic_vector (3 downto 0)\r
             );\r
     end component;\r
 \r
@@ -139,6 +139,7 @@ architecture rtl of de0_cv_nes is
         port (\r
             pi_rst_n       : in std_logic;\r
             pi_base_clk    : in std_logic;\r
+            pi_rnd_en      : in std_logic_vector (3 downto 0);\r
 \r
             --ppu i/f\r
             pi_ppu_ctrl        : in std_logic_vector (7 downto 0);\r
@@ -174,7 +175,7 @@ constant rom_32k    : integer := 15;    --32k = 15  bit width.
 constant vram_1k    : integer := 10;    --1k = 10   bit width.\r
 \r
 signal wr_cpu_en       : std_logic_vector (7 downto 0);\r
-signal wr_ppu_en       : std_logic_vector (3 downto 0);\r
+signal wr_rnd_en       : std_logic_vector (3 downto 0);\r
 \r
 signal wr_rdy       : std_logic;\r
 signal wr_irq_n     : std_logic;\r
@@ -220,7 +221,7 @@ begin
             pi_rst_n,\r
             pi_base_clk,\r
             wr_cpu_en,\r
-            wr_ppu_en\r
+            wr_rnd_en\r
             );\r
 \r
     --mos 6502 cpu instance\r
@@ -343,6 +344,7 @@ begin
     render_inst : render port map (\r
             pi_rst_n, \r
             pi_base_clk,\r
+            wr_rnd_en,\r
 \r
             --ppu i/f\r
             wr_ppu_ctrl,\r

diff --git a/de0_cv_nes/ppu/render.vhd b/de0_cv_nes/ppu/render.vhd
index deb4e46..64385c6 100644 (file)
--- a/de0_cv_nes/ppu/render.vhd
+++ b/de0_cv_nes/ppu/render.vhd
@@ -13,6 +13,7 @@ entity render is
     port (\r
         pi_rst_n       : in std_logic;\r
         pi_base_clk    : in std_logic;\r
+        pi_rnd_en      : in std_logic_vector (3 downto 0);\r
 \r
         --ppu i/f\r
         pi_ppu_ctrl        : in std_logic_vector (7 downto 0);\r
@@ -162,13 +163,56 @@ constant nes_color_palette : nes_color_array := (
         conv_std_logic_vector(16#000#, 12)\r
         );\r
 \r
-signal reg_vga_x        : std_logic_vector (9 downto 0);\r
-signal reg_vga_y        : std_logic_vector (9 downto 0);\r
+signal reg_vga_x        : integer range 0 to VGA_W_MAX - 1;\r
+signal reg_vga_y        : integer range 0 to VGA_H_MAX - 1;\r
 \r
-signal reg_nes_x        : std_logic_vector (8 downto 0);\r
-signal reg_nes_y        : std_logic_vector (8 downto 0);\r
+signal reg_nes_x        : integer range 0 to VGA_W_MAX / 2 - 1;\r
+signal reg_nes_y        : integer range 0 to VGA_W_MAX / 2 - 1;\r
 \r
 begin\r
-    \r
+\r
+    --position and sync signal generate.\r
+    pos_p : process (pi_rst_n, pi_base_clk)\r
+    begin\r
+        if (pi_rst_n = '0') then\r
+            reg_vga_x <= 0;\r
+            reg_vga_y <= 0;\r
+            reg_nes_x <= 0;\r
+            reg_nes_y <= 0;\r
+        elsif (rising_edge(pi_base_clk)) then\r
+\r
+            reg_nes_x <= reg_vga_x / 2;\r
+            reg_nes_y <= reg_vga_y / 2;\r
+\r
+            if ((pi_rnd_en(0) or pi_rnd_en(2))= '1') then\r
+                if (reg_vga_x = VGA_W_MAX - 1) then\r
+                    reg_vga_x <= 0;\r
+                    if (reg_vga_x = VGA_H_MAX - 1) then\r
+                        reg_vga_y <= 0;\r
+                    else\r
+                        reg_vga_y <= reg_vga_y + 1;\r
+                    end if;\r
+                else\r
+                    reg_vga_x <= reg_vga_x + 1;\r
+                end if;\r
+                \r
+                --sync signal assert.\r
+                if (reg_vga_x >= VGA_W + H_FP and reg_vga_x < VGA_W + H_FP + H_SP) then\r
+                    po_h_sync_n <= '0';\r
+                else\r
+                    po_h_sync_n <= '1';\r
+                end if;\r
+\r
+                if (reg_vga_y >= VGA_H + V_FP and reg_vga_y < VGA_H + V_FP + V_SP) then\r
+                    po_v_sync_n <= '0';\r
+                else\r
+                    po_v_sync_n <= '1';\r
+                end if;\r
+                \r
+            end if;--if (pi_rnd_en(1) = '1' or pi_rnd_en(3) = '1' ) then\r
+        end if;--if (pi_rst_n = '0') then\r
+    end process;\r
+\r
+\r
 end rtl;\r
 \r

diff --git a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
index a550c20..b8a936f 100644 (file)
--- a/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
+++ b/de0_cv_nes/simulation/modelsim/de0_cv_nes_run_msim_rtl_vhdl.do
@@ -9,6 +9,7 @@ vcom -93 -work work {../../chip_selector.vhd}
 vcom -93 -work work {../../mem/ram.vhd}\r
 vcom -93 -work work {../../mem/chr_rom.vhd}\r
 vcom -93 -work work {../../ppu/ppu.vhd}\r
+vcom -93 -work work {../../ppu/render.vhd}\r
 vcom -93 -work work {../../dummy-mos6502.vhd}\r
 \r
 vcom -93 -work work {../../de0_cv_nes.vhd}\r
@@ -44,6 +45,21 @@ add wave -label v_wr_n        -radix hex sim:/testbench_motones_sim/sim_board/wr
 add wave -label vram_addr        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_addr;\r
 add wave -label vram_data        -radix hex sim:/testbench_motones_sim/sim_board/wr_v_data;\r
 \r
+add wave -divider render\r
+add wave -label vga_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_x;\r
+add wave -label vga_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_vga_y;\r
+add wave -label nes_x       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_x;\r
+add wave -label nes_y       sim:/testbench_motones_sim/sim_board/render_inst/reg_nes_y;\r
+\r
+\r
+add wave -divider vga\r
+add wave -label h_sync_n       sim:/testbench_motones_sim/sim_board/po_h_sync_n;\r
+add wave -label v_sync_n    sim:/testbench_motones_sim/sim_board/po_v_sync_n;\r
+add wave -label r       sim:/testbench_motones_sim/sim_board/po_r;\r
+add wave -label g       sim:/testbench_motones_sim/sim_board/po_g;\r
+add wave -label b       sim:/testbench_motones_sim/sim_board/po_b;\r
+\r
+\r
 #add wave -radix hex sim:/testbench_motones_sim/sim_board/vram_plt_inst/*;\r
 \r
 \r