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qed: Enable automatic recovery on error condition.
authorAlok Prasad <palok@marvell.com>
Tue, 24 Aug 2021 04:02:46 +0000 (04:02 +0000)
committerDavid S. Miller <davem@davemloft.net>
Wed, 25 Aug 2021 09:38:16 +0000 (10:38 +0100)
This patch enables automatic recovery by default in case of various
error condition like fw assert , hardware error etc.
This also ensure driver can handle multiple iteration of assertion
conditions.

Signed-off-by: Ariel Elior <aelior@marvell.com>
Signed-off-by: Shai Malin <smalin@marvell.com>
Signed-off-by: Igor Russkikh <irusskikh@marvell.com>
Signed-off-by: Alok Prasad <palok@marvell.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/qlogic/qed/qed_devlink.c
drivers/net/ethernet/qlogic/qed/qed_int.c
drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
drivers/net/ethernet/qlogic/qede/qede_main.c

index 4c7501b..7807068 100644 (file)
@@ -93,7 +93,7 @@ static const struct devlink_health_reporter_ops qed_fw_fatal_reporter_ops = {
                .dump = qed_fw_fatal_reporter_dump,
 };
 
-#define QED_REPORTER_FW_GRACEFUL_PERIOD 1200000
+#define QED_REPORTER_FW_GRACEFUL_PERIOD 0
 
 void qed_fw_reporters_create(struct devlink *devlink)
 {
index ab6d4f7..f78e605 100644 (file)
@@ -351,6 +351,9 @@ static int qed_fw_assertion(struct qed_hwfn *p_hwfn)
        qed_hw_err_notify(p_hwfn, p_hwfn->p_dpc_ptt, QED_HW_ERR_FW_ASSERT,
                          "FW assertion!\n");
 
+       /* Clear assert indications */
+       qed_wr(p_hwfn, p_hwfn->p_dpc_ptt, MISC_REG_AEU_GENERAL_ATTN_32, 0);
+
        return -EINVAL;
 }
 
@@ -953,6 +956,13 @@ qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
        DP_INFO(p_hwfn, "`%s' - Disabled future attentions\n",
                p_bit_name);
 
+       /* Re-enable FW aassertion (Gen 32) interrupts */
+       val = qed_rd(p_hwfn, p_hwfn->p_dpc_ptt,
+                    MISC_REG_AEU_ENABLE4_IGU_OUT_0);
+       val |= MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32;
+       qed_wr(p_hwfn, p_hwfn->p_dpc_ptt,
+              MISC_REG_AEU_ENABLE4_IGU_OUT_0, val);
+
 out:
        return rc;
 }
index 9db22be..da1b7fd 100644 (file)
        0x180824UL
 #define  MISC_REG_AEU_GENERAL_ATTN_0 \
        0x008400UL
+#define MISC_REG_AEU_GENERAL_ATTN_32 \
+       0x008480UL
 #define MISC_REG_AEU_GENERAL_ATTN_35 \
        0x00848cUL
 #define  CAU_REG_SB_ADDR_MEMORY \
        0x180804UL
 #define  MISC_REG_AEU_ENABLE1_IGU_OUT_0 \
        0x00849cUL
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_0 \
+       0x0084a8UL
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32      \
+       (0x1UL << 0)
+#define MISC_REG_AEU_ENABLE4_IGU_OUT_0_GENERAL_ATTN32_SHIFT \
+       0
 #define MISC_REG_AEU_AFTER_INVERT_1_IGU        \
        0x0087b4UL
 #define  MISC_REG_AEU_MASK_ATTN_IGU \
index d400e9b..4877cb8 100644 (file)
@@ -1898,6 +1898,12 @@ static int qede_req_msix_irqs(struct qede_dev *edev)
                                 &edev->fp_array[i]);
                if (rc) {
                        DP_ERR(edev, "Request fp %d irq failed\n", i);
+#ifdef CONFIG_RFS_ACCEL
+                       if (edev->ndev->rx_cpu_rmap)
+                               free_irq_cpu_rmap(edev->ndev->rx_cpu_rmap);
+
+                       edev->ndev->rx_cpu_rmap = NULL;
+#endif
                        qede_sync_free_irqs(edev);
                        return rc;
                }
@@ -2290,6 +2296,15 @@ static void qede_unload(struct qede_dev *edev, enum qede_unload_mode mode,
 
                rc = qede_stop_queues(edev);
                if (rc) {
+#ifdef CONFIG_RFS_ACCEL
+                       if (edev->dev_info.common.b_arfs_capable) {
+                               qede_poll_for_freeing_arfs_filters(edev);
+                               if (edev->ndev->rx_cpu_rmap)
+                                       free_irq_cpu_rmap(edev->ndev->rx_cpu_rmap);
+
+                               edev->ndev->rx_cpu_rmap = NULL;
+                       }
+#endif
                        qede_sync_free_irqs(edev);
                        goto out;
                }
@@ -2620,8 +2635,10 @@ static void qede_generic_hw_err_handler(struct qede_dev *edev)
                  "Generic sleepable HW error handling started - err_flags 0x%lx\n",
                  edev->err_flags);
 
-       if (edev->devlink)
+       if (edev->devlink) {
+               DP_NOTICE(edev, "Reporting fatal error to devlink\n");
                edev->ops->common->report_fatal_error(edev->devlink, edev->last_err_type);
+       }
 
        clear_bit(QEDE_ERR_IS_HANDLED, &edev->err_flags);
 
@@ -2643,6 +2660,8 @@ static void qede_set_hw_err_flags(struct qede_dev *edev,
        case QED_HW_ERR_FW_ASSERT:
                set_bit(QEDE_ERR_ATTN_CLR_EN, &err_flags);
                set_bit(QEDE_ERR_GET_DBG_INFO, &err_flags);
+               /* make this error as recoverable and start recovery*/
+               set_bit(QEDE_ERR_IS_RECOVERABLE, &err_flags);
                break;
 
        default: