drm/amd/display: really fix time out in init sequence

REG_UPDATE_2 return the reg value it write out through MMIO
we need to do a REG_READ to confirm the value is written out

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
index 1984ac2..2d843b2 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c
@@ -42,13 +42,14 @@ void hubp1_set_blank(struct hubp *hubp, bool blank)
 {
        struct dcn10_hubp *hubp1 = TO_DCN10_HUBP(hubp);
        uint32_t blank_en = blank ? 1 : 0;
-       uint32_t reg_val = 0;
 
-       reg_val = REG_UPDATE_2(DCHUBP_CNTL,
+       REG_UPDATE_2(DCHUBP_CNTL,
                        HUBP_BLANK_EN, blank_en,
                        HUBP_TTU_DISABLE, blank_en);
 
        if (blank) {
+               uint32_t reg_val = REG_READ(DCHUBP_CNTL);
+
                if (reg_val) {
                        /* init sequence workaround: in case HUBP is
                         * power gated, this wait would timeout.