if (N0.getOpcode() == ISD::AND && N0.getNode()->hasOneUse() &&
N0->getOperand(1) == N1) {
SDValue X = N0->getOperand(0);
- SDValue NotX = DAG.getNode(ISD::XOR, X.getDebugLoc(), VT, X,
- DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT));
+ SDValue NotX = DAG.getNOT(X.getDebugLoc(), X, VT);
AddToWorkList(NotX.getNode());
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NotX, N1);
}
; X32: notl [[REG:%[a-z]+]]
; X32: andl {{.*}}[[REG:%[a-z]+]]
}
+
+; PR15948
+define <4 x i32> @test10(<4 x i32> %a) nounwind {
+ %1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
+ %2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
+ ret <4 x i32> %2
+; X64: test10:
+; X64: andnps
+; X32: test10:
+; X32: andnps
+}