.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
- .dbuf.size = 896, \
+ .dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \
.dbuf.num_slices = 1
#define SKL_PLATFORM \
static const struct intel_device_info bxt_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_BROXTON),
- .dbuf.size = 512,
+ .dbuf.size = 512 - 4, /* 4 blocks for bypass path allocation */
};
static const struct intel_device_info glk_info = {
GEN9_LP_FEATURES,
PLATFORM(INTEL_GEMINILAKE),
.display.ver = 10,
- .dbuf.size = 1024,
+ .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */
GLK_COLORS,
};
#define GEN10_FEATURES \
GEN9_FEATURES, \
GEN(10), \
- .dbuf.size = 1024, \
+ .dbuf.size = 1024 - 4, /* 4 blocks for bypass path allocation */ \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
GLK_COLORS
static int intel_dbuf_size(struct drm_i915_private *dev_priv)
{
- int ddb_size = INTEL_INFO(dev_priv)->dbuf.size;
-
- drm_WARN_ON(&dev_priv->drm, ddb_size == 0);
-
- if (DISPLAY_VER(dev_priv) < 11)
- return ddb_size - 4; /* 4 blocks for bypass path allocation */
-
- return ddb_size;
+ return INTEL_INFO(dev_priv)->dbuf.size;
}
static int intel_dbuf_slice_size(struct drm_i915_private *dev_priv)