#ifndef _ASM_EFI_H
#define _ASM_EFI_H
-#include <asm/cpufeature.h>
#include <asm/io.h>
#include <asm/mmu_context.h>
#include <asm/neon.h>
static inline void efi_set_pgd(struct mm_struct *mm)
{
- __switch_mm(mm);
-
- if (system_uses_ttbr0_pan()) {
- if (mm != current->active_mm) {
- /*
- * Update the current thread's saved ttbr0 since it is
- * restored as part of a return from exception. Set
- * the hardware TTBR0_EL1 using cpu_switch_mm()
- * directly to enable potential errata workarounds.
- */
- update_saved_ttbr0(current, mm);
- cpu_switch_mm(mm->pgd, mm);
- } else {
- /*
- * Defer the switch to the current thread's TTBR0_EL1
- * until uaccess_enable(). Restore the current
- * thread's saved ttbr0 corresponding to its active_mm
- * (if different from init_mm).
- */
- cpu_set_reserved_ttbr0();
- if (current->active_mm != &init_mm)
- update_saved_ttbr0(current, current->active_mm);
- }
- }
+ switch_mm(NULL, mm, NULL);
}
void efi_virtmap_load(void);
#include <linux/sched.h>
#include <asm/cacheflush.h>
-#include <asm/cpufeature.h>
#include <asm/proc-fns.h>
#include <asm-generic/mm_hooks.h>
#include <asm/cputype.h>
local_flush_tlb_all();
cpu_set_default_tcr_t0sz();
- if (mm != &init_mm && !system_uses_ttbr0_pan())
+ if (mm != &init_mm)
cpu_switch_mm(mm->pgd, mm);
}
{
}
-#ifdef CONFIG_ARM64_SW_TTBR0_PAN
-static inline void update_saved_ttbr0(struct task_struct *tsk,
- struct mm_struct *mm)
-{
- if (system_uses_ttbr0_pan()) {
- BUG_ON(mm->pgd == swapper_pg_dir);
- task_thread_info(tsk)->ttbr0 =
- virt_to_phys(mm->pgd) | ASID(mm) << 48;
- }
-}
-#else
-static inline void update_saved_ttbr0(struct task_struct *tsk,
- struct mm_struct *mm)
-{
-}
-#endif
-
-static inline void __switch_mm(struct mm_struct *next)
+/*
+ * This is the actual mm switch as far as the scheduler
+ * is concerned. No registers are touched. We avoid
+ * calling the CPU specific function when the mm hasn't
+ * actually changed.
+ */
+static inline void
+switch_mm(struct mm_struct *prev, struct mm_struct *next,
+ struct task_struct *tsk)
{
unsigned int cpu = smp_processor_id();
+ if (prev == next)
+ return;
+
/*
* init_mm.pgd does not contain any user mappings and it is always
* active for kernel addresses in TTBR1. Just set the reserved TTBR0.
check_and_switch_context(next, cpu);
}
-static inline void
-switch_mm(struct mm_struct *prev, struct mm_struct *next,
- struct task_struct *tsk)
-{
- if (prev != next)
- __switch_mm(next);
-
- /*
- * Update the saved TTBR0_EL1 of the scheduled-in task as the previous
- * value may have not been initialised yet (activate_mm caller) or the
- * ASID has changed since the last run (following the context switch
- * of another thread of the same process).
- */
- update_saved_ttbr0(tsk, next);
-}
-
#define deactivate_mm(tsk,mm) do { } while (0)
-#define activate_mm(prev,next) switch_mm(prev, next, current)
+#define activate_mm(prev,next) switch_mm(prev, next, NULL)
#endif
#include <uapi/asm/ptrace.h>
-#define _PSR_PAN_BIT 22
-
/* Current Exception Level values, as contained in CurrentEL */
#define CurrentEL_EL1 (1 << 2)
#define CurrentEL_EL2 (2 << 2)
#include <asm/esr.h>
#include <asm/irq.h>
#include <asm/memory.h>
-#include <asm/ptrace.h>
#include <asm/thread_info.h>
-#include <asm/uaccess.h>
#include <asm/unistd.h>
/*
mrs x22, elr_el1
mrs x23, spsr_el1
stp lr, x21, [sp, #S_LR]
-
-#ifdef CONFIG_ARM64_SW_TTBR0_PAN
- /*
- * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
- * EL0, there is no need to check the state of TTBR0_EL1 since
- * accesses are always enabled.
- * Note that the meaning of this bit differs from the ARMv8.1 PAN
- * feature as all TTBR0_EL1 accesses are disabled, not just those to
- * user mappings.
- */
-alternative_if_not ARM64_HAS_PAN
- nop
-alternative_else
- b 1f // skip TTBR0 PAN
-alternative_endif
-
- .if \el != 0
- mrs x21, ttbr0_el1
- tst x21, #0xffff << 48 // Check for the reserved ASID
- orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
- b.eq 1f // TTBR0 access already disabled
- and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
- .endif
-
- uaccess_ttbr0_disable x21
-1:
-#endif
-
stp x22, x23, [sp, #S_PC]
/*
ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
.if \el == 0
ct_user_enter
- .endif
-
-#ifdef CONFIG_ARM64_SW_TTBR0_PAN
- /*
- * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
- * PAN bit checking.
- */
-alternative_if_not ARM64_HAS_PAN
- nop
-alternative_else
- b 2f // skip TTBR0 PAN
-alternative_endif
-
- .if \el != 0
- tbnz x22, #_PSR_PAN_BIT, 1f // Skip re-enabling TTBR0 access if previously disabled
- .endif
-
- uaccess_ttbr0_enable x0
-
- .if \el == 0
- /*
- * Enable errata workarounds only if returning to user. The only
- * workaround currently required for TTBR0_EL1 changes are for the
- * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
- * corruption).
- */
- post_ttbr0_update_workaround
- .endif
-1:
- .if \el != 0
- and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
- .endif
-2:
-#endif
-
- .if \el == 0
ldr x23, [sp, #S_SP] // load return stack pointer
msr sp_el0, x23
#ifdef CONFIG_ARM64_ERRATUM_845719
alternative_endif
#endif
.endif
-
msr elr_el1, x21 // set up the return data
msr spsr_el1, x22
ldp x0, x1, [sp, #16 * 0]
smp_init_cpus();
smp_build_mpidr_hash();
-#ifdef CONFIG_ARM64_SW_TTBR0_PAN
- /*
- * Make sure init_thread_info.ttbr0 always generates translation
- * faults in case uaccess_enable() is inadvertently called by the init
- * thread.
- */
- init_thread_info.ttbr0 = virt_to_phys(empty_zero_page);
-#endif
-
#ifdef CONFIG_VT
#if defined(CONFIG_VGA_CONSOLE)
conswitchp = &vga_con;
raw_spin_unlock_irqrestore(&cpu_asid_lock, flags);
switch_mm_fastpath:
- /*
- * Defer TTBR0_EL1 setting for user threads to uaccess_enable() when
- * emulating PAN.
- */
- if (!system_uses_ttbr0_pan())
- cpu_switch_mm(mm->pgd, mm);
+ cpu_switch_mm(mm->pgd, mm);
}
static int asids_init(void)
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