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soc: imx: add i.MX8MP HDMI blk ctrl HDCP/HRV_MWR
authorPeng Fan <peng.fan@nxp.com>
Mon, 22 Aug 2022 06:45:33 +0000 (14:45 +0800)
committerShawn Guo <shawnguo@kernel.org>
Sat, 17 Sep 2022 08:30:53 +0000 (16:30 +0800)
i.MX8MP HDMI supports HDCP and HRV_MWR(HDMI RX Video Memory Write Master
for RXRX validation), so add them.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
drivers/soc/imx/imx8mp-blk-ctrl.c

index 6f983ad..527d45d 100644 (file)
@@ -235,6 +235,13 @@ static void imx8mp_hdmi_blk_ctrl_power_on(struct imx8mp_blk_ctrl *bc,
                regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
                regmap_clear_bits(bc->regmap, HDMI_TX_CONTROL0, BIT(3));
                break;
+       case IMX8MP_HDMIBLK_PD_HDCP:
+               regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
+               break;
+       case IMX8MP_HDMIBLK_PD_HRV:
+               regmap_set_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
+               regmap_set_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
+               break;
        default:
                break;
        }
@@ -283,6 +290,13 @@ static void imx8mp_hdmi_blk_ctrl_power_off(struct imx8mp_blk_ctrl *bc,
                regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(12));
                regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(22) | BIT(24));
                break;
+       case IMX8MP_HDMIBLK_PD_HDCP:
+               regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL0, BIT(11));
+               break;
+       case IMX8MP_HDMIBLK_PD_HRV:
+               regmap_clear_bits(bc->regmap, HDMI_RTX_RESET_CTL0, BIT(15));
+               regmap_clear_bits(bc->regmap, HDMI_RTX_CLK_CTL1, BIT(3) | BIT(4) | BIT(5));
+               break;
        default:
                break;
        }
@@ -365,6 +379,22 @@ static const struct imx8mp_blk_ctrl_domain_data imx8mp_hdmi_domain_data[] = {
                .num_clks = 2,
                .gpc_name = "hdmi-tx-phy",
        },
+       [IMX8MP_HDMIBLK_PD_HRV] = {
+               .name = "hdmiblk-hrv",
+               .clk_names = (const char *[]){ "axi", "apb" },
+               .num_clks = 2,
+               .gpc_name = "hrv",
+               .path_names = (const char *[]){"hrv"},
+               .num_paths = 1,
+       },
+       [IMX8MP_HDMIBLK_PD_HDCP] = {
+               .name = "hdmiblk-hdcp",
+               .clk_names = (const char *[]){ "axi", "apb" },
+               .num_clks = 2,
+               .gpc_name = "hdcp",
+               .path_names = (const char *[]){"hdcp"},
+               .num_paths = 1,
+       },
 };
 
 static const struct imx8mp_blk_ctrl_data imx8mp_hdmi_blk_ctl_dev_data = {