OSDN Git Service

drm/amdgpu: indirect register access for nv12 sriov
authorPeng Ju Zhou <PengJu.Zhou@amd.com>
Mon, 29 Mar 2021 07:47:20 +0000 (15:47 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Fri, 9 Apr 2021 20:50:09 +0000 (16:50 -0400)
get pf2vf msg info at it's earliest time so that
guest driver can use these info to decide whether
register indirect access enabled.

Signed-off-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
Reviewed-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c

index a501d1a..060d0ae 100644 (file)
@@ -2080,6 +2080,11 @@ static int amdgpu_device_ip_early_init(struct amdgpu_device *adev)
                                amdgpu_vf_error_put(adev, AMDGIM_ERROR_VF_ATOMBIOS_INIT_FAIL, 0, 0);
                                return r;
                        }
+
+                       /*get pf2vf msg info at it's earliest time*/
+                       if (amdgpu_sriov_vf(adev))
+                               amdgpu_virt_init_data_exchange(adev);
+
                }
        }
 
index d9ffff8..b62f134 100644 (file)
@@ -617,6 +617,14 @@ void amdgpu_virt_init_data_exchange(struct amdgpu_device *adev)
                                if (adev->virt.ras_init_done)
                                        amdgpu_virt_add_bad_page(adev, bp_block_offset, bp_block_size);
                        }
+       } else if (adev->bios != NULL) {
+               adev->virt.fw_reserve.p_pf2vf =
+                       (struct amd_sriov_msg_pf2vf_info_header *)
+                       (adev->bios + (AMD_SRIOV_MSG_PF2VF_OFFSET_KB << 10));
+
+               amdgpu_virt_read_pf2vf_data(adev);
+
+               return;
        }
 
        if (adev->virt.vf2pf_update_interval_ms != 0) {