powerpc: sstep: Add tests for addc[.] instruction

This adds test cases for the addc[.] instruction.

Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/include/asm/ppc-opcode.h b/arch/powerpc/include/asm/ppc-opcode.h
index 19a8834..87b73aa 100644 (file)
--- a/arch/powerpc/include/asm/ppc-opcode.h
+++ b/arch/powerpc/include/asm/ppc-opcode.h
@@ -326,6 +326,7 @@
 #define PPC_INST_ADDI                  0x38000000
 #define PPC_INST_ADDIS                 0x3c000000
 #define PPC_INST_ADD                   0x7c000214
+#define PPC_INST_ADDC                  0x7c000014
 #define PPC_INST_SUB                   0x7c000050
 #define PPC_INST_BLR                   0x4e800020
 #define PPC_INST_BLRL                  0x4e800021

diff --git a/arch/powerpc/lib/test_emulate_step.c b/arch/powerpc/lib/test_emulate_step.c
index ee6d5ac..9992c1e 100644 (file)
--- a/arch/powerpc/lib/test_emulate_step.c
+++ b/arch/powerpc/lib/test_emulate_step.c
@@ -53,6 +53,10 @@
                                        ___PPC_RA(a) | ___PPC_RB(b))
 #define TEST_ADD_DOT(t, a, b)  (PPC_INST_ADD | ___PPC_RT(t) |          \
                                        ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
+#define TEST_ADDC(t, a, b)     (PPC_INST_ADDC | ___PPC_RT(t) |         \
+                                       ___PPC_RA(a) | ___PPC_RB(b))
+#define TEST_ADDC_DOT(t, a, b) (PPC_INST_ADDC | ___PPC_RT(t) |         \
+                                       ___PPC_RA(a) | ___PPC_RB(b) | 0x1)
 
 #define MAX_SUBTESTS   16
 
@@ -649,6 +653,194 @@ static struct compute_test compute_tests[] = {
                                }
                        }
                }
+       },
+       {
+               .mnemonic = "addc",
+               .subtests = {
+                       {
+                               .descr = "RA = LONG_MIN, RB = LONG_MIN",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = LONG_MIN,
+                                       .gpr[22] = LONG_MIN,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MIN, RB = LONG_MAX",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = LONG_MIN,
+                                       .gpr[22] = LONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MAX, RB = LONG_MAX",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = LONG_MAX,
+                                       .gpr[22] = LONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = ULONG_MAX, RB = ULONG_MAX",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = ULONG_MAX,
+                                       .gpr[22] = ULONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = ULONG_MAX, RB = 0x1",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = ULONG_MAX,
+                                       .gpr[22] = 0x1,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MIN, RB = INT_MIN",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = INT_MIN,
+                                       .gpr[22] = INT_MIN,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MIN, RB = INT_MAX",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = INT_MIN,
+                                       .gpr[22] = INT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MAX, RB = INT_MAX",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = INT_MAX,
+                                       .gpr[22] = INT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = UINT_MAX, RB = UINT_MAX",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = UINT_MAX,
+                                       .gpr[22] = UINT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = UINT_MAX, RB = 0x1",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = UINT_MAX,
+                                       .gpr[22] = 0x1,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MIN | INT_MIN, RB = LONG_MIN | INT_MIN",
+                               .instr = TEST_ADDC(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = LONG_MIN | (uint)INT_MIN,
+                                       .gpr[22] = LONG_MIN | (uint)INT_MIN,
+                               }
+                       }
+               }
+       },
+       {
+               .mnemonic = "addc.",
+               .subtests = {
+                       {
+                               .descr = "RA = LONG_MIN, RB = LONG_MIN",
+                               .flags = IGNORE_CCR,
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = LONG_MIN,
+                                       .gpr[22] = LONG_MIN,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MIN, RB = LONG_MAX",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = LONG_MIN,
+                                       .gpr[22] = LONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MAX, RB = LONG_MAX",
+                               .flags = IGNORE_CCR,
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = LONG_MAX,
+                                       .gpr[22] = LONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = ULONG_MAX, RB = ULONG_MAX",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = ULONG_MAX,
+                                       .gpr[22] = ULONG_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = ULONG_MAX, RB = 0x1",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = ULONG_MAX,
+                                       .gpr[22] = 0x1,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MIN, RB = INT_MIN",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = INT_MIN,
+                                       .gpr[22] = INT_MIN,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MIN, RB = INT_MAX",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = INT_MIN,
+                                       .gpr[22] = INT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = INT_MAX, RB = INT_MAX",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = INT_MAX,
+                                       .gpr[22] = INT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = UINT_MAX, RB = UINT_MAX",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = UINT_MAX,
+                                       .gpr[22] = UINT_MAX,
+                               }
+                       },
+                       {
+                               .descr = "RA = UINT_MAX, RB = 0x1",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = UINT_MAX,
+                                       .gpr[22] = 0x1,
+                               }
+                       },
+                       {
+                               .descr = "RA = LONG_MIN | INT_MIN, RB = LONG_MIN | INT_MIN",
+                               .instr = TEST_ADDC_DOT(20, 21, 22),
+                               .regs = {
+                                       .gpr[21] = LONG_MIN | (uint)INT_MIN,
+                                       .gpr[22] = LONG_MIN | (uint)INT_MIN,
+                               }
+                       }
+               }
        }
 };