drm/i915/display: Fill PSR state during hardware configuration read out

So far if we had a mismatch between the state asked and what was
programmed in hardware for PSR, this mismatch would go unnoticed.

So here adding the PSR to the hardware configuration readout,
EDP_PSR_CTL and EDP_PSR2_CTL can't be directly read because its state
flips due to other factors like frontbuffer modifications and CRC.

Cc: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210418002126.87882-1-jose.souza@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 0b382e4..b7a2fce 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -3709,6 +3709,8 @@ static void intel_ddi_get_config(struct intel_encoder *encoder,
 
        intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA);
        intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC);
+
+       intel_psr_get_config(encoder, pipe_config);
 }
 
 void intel_ddi_get_clock(struct intel_encoder *encoder,

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fc7e18f..2cdc0b9 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8631,6 +8631,11 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config,
        PIPE_CONF_CHECK_I(vrr.flipline);
        PIPE_CONF_CHECK_I(vrr.pipeline_full);
 
+       PIPE_CONF_CHECK_BOOL(has_psr);
+       PIPE_CONF_CHECK_BOOL(has_psr2);
+       PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
+       PIPE_CONF_CHECK_I(dc3co_exitline);
+
 #undef PIPE_CONF_CHECK_X
 #undef PIPE_CONF_CHECK_I
 #undef PIPE_CONF_CHECK_BOOL

diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 406ba9a..acaf3d4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -901,6 +901,51 @@ void intel_psr_compute_config(struct intel_dp *intel_dp,
        crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
 }
 
+void intel_psr_get_config(struct intel_encoder *encoder,
+                         struct intel_crtc_state *pipe_config)
+{
+       struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+       struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+       struct intel_dp *intel_dp;
+       u32 val;
+
+       if (!dig_port)
+               return;
+
+       intel_dp = &dig_port->dp;
+       if (!CAN_PSR(intel_dp))
+               return;
+
+       mutex_lock(&intel_dp->psr.lock);
+       if (!intel_dp->psr.enabled)
+               goto unlock;
+
+       /*
+        * Not possible to read EDP_PSR/PSR2_CTL registers as it is
+        * enabled/disabled because of frontbuffer tracking and others.
+        */
+       pipe_config->has_psr = true;
+       pipe_config->has_psr2 = intel_dp->psr.psr2_enabled;
+       pipe_config->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC);
+
+       if (!intel_dp->psr.psr2_enabled)
+               goto unlock;
+
+       if (HAS_PSR2_SEL_FETCH(dev_priv)) {
+               val = intel_de_read(dev_priv, PSR2_MAN_TRK_CTL(intel_dp->psr.transcoder));
+               if (val & PSR2_MAN_TRK_CTL_ENABLE)
+                       pipe_config->enable_psr2_sel_fetch = true;
+       }
+
+       if (DISPLAY_VER(dev_priv) >= 12) {
+               val = intel_de_read(dev_priv, EXITLINE(intel_dp->psr.transcoder));
+               val &= EXITLINE_MASK;
+               pipe_config->dc3co_exitline = val;
+       }
+unlock:
+       mutex_unlock(&intel_dp->psr.lock);
+}
+
 static void intel_psr_activate(struct intel_dp *intel_dp)
 {
        struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);

diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0491a49..e3db85e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -17,6 +17,7 @@ struct intel_crtc;
 struct intel_atomic_state;
 struct intel_plane_state;
 struct intel_plane;
+struct intel_encoder;
 
 void intel_psr_init_dpcd(struct intel_dp *intel_dp);
 void intel_psr_enable(struct intel_dp *intel_dp,
@@ -37,6 +38,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
 void intel_psr_init(struct intel_dp *intel_dp);
 void intel_psr_compute_config(struct intel_dp *intel_dp,
                              struct intel_crtc_state *crtc_state);
+void intel_psr_get_config(struct intel_encoder *encoder,
+                         struct intel_crtc_state *pipe_config);
 void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir);
 void intel_psr_short_pulse(struct intel_dp *intel_dp);
 void intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);