OSDN Git Service
(root)
/
uclinux-h8
/
linux.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
| inline |
side by side
(parent:
6455239
)
perf/x86/intel: Add Broadwell support for the LBR callstack
author
Kan Liang
<kan.liang@intel.com>
Thu, 2 Apr 2015 08:12:57 +0000
(
04:12
-0400)
committer
Ingo Molnar
<mingo@kernel.org>
Fri, 17 Apr 2015 07:59:07 +0000
(09:59 +0200)
Same as Haswell, Broadwell also support the LBR callstack.
Signed-off-by: Kan Liang <kan.liang@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Acked-by: Andi Kleen <ak@linux.intel.com>
Link:
http://lkml.kernel.org/r/1427962377-40955-1-git-send-email-kan.liang@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/kernel/cpu/perf_event_intel.c
patch
|
blob
|
history
diff --git
a/arch/x86/kernel/cpu/perf_event_intel.c
b/arch/x86/kernel/cpu/perf_event_intel.c
index
9da2400
..
219d3fb
100644
(file)
--- a/
arch/x86/kernel/cpu/perf_event_intel.c
+++ b/
arch/x86/kernel/cpu/perf_event_intel.c
@@
-3275,7
+3275,7
@@
__init int intel_pmu_init(void)
hw_cache_extra_regs[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = HSW_DEMAND_WRITE|
BDW_L3_MISS_LOCAL|HSW_SNOOP_DRAM;
- intel_pmu_lbr_init_
snb
();
+ intel_pmu_lbr_init_
hsw
();
x86_pmu.event_constraints = intel_bdw_event_constraints;
x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints;