drm/amdgpu: add soc15 common ip block support for aldebaran

Initialize aldebaran common ip block

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Acked-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index a75e150..de45fe1 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -923,7 +923,8 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                adev->nbio.funcs = &nbio_v7_0_funcs;
                adev->nbio.hdp_flush_reg = &nbio_v7_0_hdp_flush_reg;
        } else if (adev->asic_type == CHIP_VEGA20 ||
-                  adev->asic_type == CHIP_ARCTURUS) {
+                  adev->asic_type == CHIP_ARCTURUS ||
+                  adev->asic_type == CHIP_ALDEBARAN) {
                adev->nbio.funcs = &nbio_v7_4_funcs;
                adev->nbio.hdp_flush_reg = &nbio_v7_4_hdp_flush_reg;
        } else {
@@ -932,7 +933,9 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
        }
        adev->hdp.funcs = &hdp_v4_0_funcs;
 
-       if (adev->asic_type == CHIP_VEGA20 || adev->asic_type == CHIP_ARCTURUS)
+       if (adev->asic_type == CHIP_VEGA20 ||
+           adev->asic_type == CHIP_ARCTURUS ||
+           adev->asic_type == CHIP_ALDEBARAN)
                adev->df.funcs = &df_v3_6_funcs;
        else
                adev->df.funcs = &df_v1_7_funcs;
@@ -1059,6 +1062,13 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)
                amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
                amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
                break;
+       case CHIP_ALDEBARAN:
+               amdgpu_device_ip_block_add(adev, &vega10_common_ip_block);
+               amdgpu_device_ip_block_add(adev, &gmc_v9_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &vega10_ih_ip_block);
+               amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block);
+               amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block);
+               break;
        default:
                return -EINVAL;
        }
@@ -1479,6 +1489,11 @@ static int soc15_common_early_init(void *handle)
                                 AMD_PG_SUPPORT_JPEG |
                                 AMD_PG_SUPPORT_VCN_DPG;
                break;
+       case CHIP_ALDEBARAN:
+               adev->asic_funcs = &vega20_asic_funcs;
+               adev->cg_flags = 0;
+               adev->pg_flags = 0;
+               break;
        default:
                /* FIXME: not supported yet */
                return -EINVAL;