static void flush_fifo_rx(struct ux500_msp *msp)
{
- u32 reg_val_DR, reg_val_GCR, reg_val_FLR;
+ u32 reg_val_GCR, reg_val_FLR;
u32 limit = 32;
reg_val_GCR = readl(msp->registers + MSP_GCR);
reg_val_FLR = readl(msp->registers + MSP_FLR);
while (!(reg_val_FLR & RX_FIFO_EMPTY) && limit--) {
- reg_val_DR = readl(msp->registers + MSP_DR);
+ readl(msp->registers + MSP_DR);
reg_val_FLR = readl(msp->registers + MSP_FLR);
}
static void flush_fifo_tx(struct ux500_msp *msp)
{
- u32 reg_val_TSTDR, reg_val_GCR, reg_val_FLR;
+ u32 reg_val_GCR, reg_val_FLR;
u32 limit = 32;
reg_val_GCR = readl(msp->registers + MSP_GCR);
reg_val_FLR = readl(msp->registers + MSP_FLR);
while (!(reg_val_FLR & TX_FIFO_EMPTY) && limit--) {
- reg_val_TSTDR = readl(msp->registers + MSP_TSTDR);
+ readl(msp->registers + MSP_TSTDR);
reg_val_FLR = readl(msp->registers + MSP_FLR);
}
writel(0x0, msp->registers + MSP_ITCR);